Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-11
2006-07-11
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S263000, C438S265000
Reexamination Certificate
active
07074674
ABSTRACT:
A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.
REFERENCES:
patent: 5930628 (1999-07-01), Chang
patent: 6678190 (2004-01-01), Yang et al.
patent: 7015100 (2006-03-01), Lee et al.
Chang Ko-Hsing
Chen Tung-Po
Hsue Chen-Chiu
Lai Tung-Ming
Chen Jack
Jianq Chyun IP Office
Powerchip Semiconductor Corp.
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