Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-22
2003-07-15
Wille, Douglas A. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S315000
Reexamination Certificate
active
06593186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a structure of a memory cell and a method manufacturing such a memory cell structure.
2. Description of the Related Art
FIG. 18
is a cross-sectional view of a general floating-gate type non-volatile semiconductor memory device of the past. In this device, field insulation film
101
on the surface of a p-type substrate
100
is used to electrically separate a memory cell region from a neighboring memory cell region, an n-type source
109
and drain
110
being formed, and a memory channel region
113
being formed so as to be sandwiched between this source and drain. On the channel region
113
a floating gate
103
is formed, with an intervening first gate insulation film
102
therebetween, and on this floating gate
103
, a control gate
112
is formed, with an intervening second gate insulation film
111
therebetween.
The method of manufacturing the above-noted structure is to form on the silicon substrate
100
the field insulation film
101
, the first gate insulation film
102
, and the channel region
113
, after which polysilicon is deposited onto the surface, this then being processed to form the shape of a floating gate. Then, an n-type dopant is introduced, so as to form the floating gate
103
, the drain
110
, and the source
109
. Onto this surface a silicon oxide film is formed by thermal oxidation, and a second gate insulation film
111
is formed by either this silicon oxide film only, or by this film laminated together with a silicon nitride film. Additionally, the control gate
112
is formed, thereby forming a stacked-gate non-volatile semiconductor memory device.
The writing characteristics of a non-volatile semiconductor memory device are determined by the junction capacitance due to the first gate insulation film
102
between the channel region
113
and the floating gate
103
, and the junction capacitance between the floating gate
103
and the control gate
112
due to the second gate insulation film
111
, and to effectively increase the voltage that is applied to the floating gate
103
, it is necessary to make the junction capacitance between the floating gate
103
and control gate
112
due to the second gate insulation film
111
large.
A method of accommodating this is to have the floating gate extend in a planar manner on the field insulation film. For this reason, it was difficult to achieve a high capacity in a stacked-gate type semiconductor memory device.
Because of the above, a structure, such as shown in
FIG. 17
, has been invented and disclosed in the Japanese Unexamined Patent Publication No.4-74477, wherein in a floating gate type semiconductor memory device formed by a floating gate
203
formed with an intervening first gate insulation film
202
on a semiconductor substrate
100
and a control gate
212
that is capacitively coupled to the floating gate
203
via a second gate insulation film
211
, this device having deep trench-shaped floating gate formed by a trench shape that reflects the shape of the underlayer, a second gate insulation film being formed on at least the inner wall surface part of the trench shape of the floating gate.
However, when forming a trench shape such as shown in FIG.
17
and
FIG. 18
in the floating gate polysilicon films
211
and
111
, it was not possible to form more than one trench for each photolithography process. For this reason, the junction capacitance between the floating gate and the control gate is determined according to depth of the trench, making it impossible to achieve an increase in capacitance.
Accordingly, it is an object of the present invention to provide an improvement over the drawbacks as noted above in the prior art, by providing in particular a novel non-volatile semiconductor memory device in which alternate films of silicon oxide and silicon nitride are formed and etch back is performed to formed a hard mask, thereby forming a trench shape that has two or more trenches that form a self-aligned floating gate, a second gate insulation film and control gate being formed therealong, so that the junction capacitance between the control gate and the floating gate is increased, the result being the achievement of low-voltage, high-speed operation. An additional object of the present invention is provide a method of manufacturing the above-noted non-volatile semiconductor memory device.
SUMMARY OF THE INVENTION
In order to achieve the above-noted object, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of the present invention is a non-volatile semiconductor memory device that has a floating gate that is formed onto a semiconductor substrate with intervening a first gate insulation film therebetween, a second gate insulation film that is formed on this floating gate, and a control gate that is provided over the second gate insulation film, wherein at least two trenches are formed in the above-noted floating gate.
In a second aspect of the present invention, at least one of the trenches is deeper than a trench that is formed to reflect the shape of the underlayer.
In a third aspect of the present invention, a drain-source region is formed so as to be parallel to the above-noted trenches.
In a fourth aspect of the present invention, the drain-source region is formed so as to be perpendicular to the above-noted trenches.
The first aspect of a method of manufacturing a non-volatile semiconductor memory device according to the present invention is a method comprising, a first step of sequentially depositing in an element forming region, a first gate oxide film
2
, a polysilicon film
3
, a first silicon oxide film
4
, and a first silicon nitride film
5
, in that sequence (FIG.
2
(
a
)), a second step of processing said first silicon nitride film
5
to a prescribed shape and expose said first silicon oxide film
4
(FIG.
2
(
b
)), a third step of sequentially forming onto a side wall of said first silicon nitride film
5
, a second silicon oxide film
6
, a second silicon nitride film
7
, and a third silicon oxide film
8
, so as to form a side wall and expose said polysilicon film
3
(FIG.
3
(
b
)), a fourth step of etching said exposed polysilicon film
3
(FIG.
3
(
c
)), a fifth step of removing said first and second silicon nitride film
5
,
7
(FIG.
3
(
c
)), a sixth step of removing said exposed silicon oxide film
4
(FIG.
4
(
a
)), and a seventh step of using said second and third silicon oxide film
6
,
8
on said polysilicon film
3
as a mask, and etching said polysilicon film
3
, thereby forming said floating gate that has a trench (FIG.
4
(
c
)).
A second aspect of a method of manufacturing a non-volatile semiconductor memory device according to the present invention is a method comprising, a first step of sequentially depositing in an element forming region, a first gate oxide film
2
, a polysilicon film
3
, a first silicon oxide film
4
, a first silicon nitride film
5
, and a second silicon oxide film
6
in this sequence (FIG.
12
(
a
)), a second step of processing said second silicon oxide film
6
to a prescribed shape and expose said first silicon nitride film
5
(FIG.
12
(
b
)), a third step of forming onto a side wall of said second silicon oxide film
6
a second silicon nitride film
7
side wall (FIG.
12
(
c
)), a fourth step of removing said second silicon oxide film
6
(FIG.
13
(
a
)), a fifth step of forming a third silicon oxide film
8
side wall on both sides of the remaining said second silicon nitride film
7
(FIG.
13
(
b
)), a sixth step of removing said exposed first silicon nitride film
5
and said second silicon nitride film
7
and expose said first silicon oxide film
4
(FIG.
13
(
c
)), a seventh step of removing said exposed first silicon oxide film
4
, and an eighth step of using said first silicon oxide film
4
, said first silicon nitride film
5
, and said third silicon oxide film
8
on said poly
Kitamura Takuya
Koga Hiroki
McGinn & Gibb PLLC
NEC Electronics Corporation
Wille Douglas A.
LandOfFree
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