Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-18
2002-10-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S263000, C438S264000
Reexamination Certificate
active
06468861
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a non-volatile semiconductor memory of high density and high reliability and to a novel structure of the non-volatile semiconductor memory formed thereby.
2. Description of the Related Art
In the non-volatile semiconductor memory, the most wide-spreading configuration is a flash memory or EEPROM constructed of a non-volatile semiconductor memory cell having a floating gate and a control gate on the channel region of a transistor. A problem of this non-volatile semiconductor memory is that a memory capacity cannot be increased.
In order to increase the memory capacity, Japanese Laid Open Patent H02-231772 A, for example, proposes that a memory cell transistor be formed more densely. According to this prior art, a plurality of rows of a first floating gate layer and a first word line layer serving as a control gate are arranged so as to intersect a bit line defused layer formed in a striped shape. Between the arrangements of the first floating gate layer and the first word line layer, a second floating gate layer is formed and then a second word line layer serving as a control gate is formed thereon. The floating gate type non-volatile semiconductor memory of this configuration forms the second floating gate layer and the second word line layer between the first floating gate layer and the first word line layer adjacent each other so that the memory cell can be formed more high-densely compared with the conventional case of arranging a plurality of rows of the first floating gate layer and the first word line layer. That is, the doubled number of word lines can be arranged in the same area without changing a design rule.
A manufacturing method described in this prior art comprises:
(1) a process for forming a first layer polycrystalline silicon film in a pattern having a plurality of stripe shapes by depositing the first layer polycrystalline silicon film on a first conductive type semiconductor substrate through an insulating film;
(2) a process for forming a wiring layer in a plurality of stripe shapes by defusing impurities using the first layer polycrystalline silicon film pattern-formed as a mask;
(3) a process for forming a plurality of first word lines and a first floating gate, the first floating gate being self-aligned therewith and arranged thereunder, by forming an insulating film on said first layer polycrystalline silicon film to deposit a second layer polycrystalline silicon film throughout thereon and by selectively etching the second layer polycrystalline silicon film and then the first layer polycrystalline silicon film using a stripe-shaped pattern mask, the stripe in the mask running in the direction intersecting said wiring layer;
(4) a process for forming a third layer polycrystalline silicon film so as to intersect the first word lines and to overlap the first floating gate by depositing the third layer polycrystalline silicon film on said first word lines through an insulating film; and
(5) a process for forming a plurality of second word lines and a second floating gate, the second floating gate being self-aligned therewith and arranged thereunder, by forming an insulating film on said third layer polycrystalline silicon film to deposit a fourth layer polycrystalline silicon film throughout thereon and by selectively etching the fourth layer polycrystalline silicon film and then the third layer polycrystalline silicon film using a stripe-shaped pattern mask that overlaps said first word lines.
According to this manufacturing method, the two-layer structures constructed of the second word line and the second floating gate are further inserted between the two-layer structures constructed of the first word line and the first floating gate in the lateral direction. Thereby, the doubled density of the memory cells is practically realized with the conventional pitch of the first word lines maintained.
The operation of this floating gate type non-volatile memory has a data writing (program) mode and a batch-erasing mode. The data writing mode is conducted by applying a predetermined voltage on a selected pair of adjacent bit lines and a selected word line to inject hot electrons into the floating gate from the substrate. The batch-erasing mode is conducted by applying a high voltage on all the bit lines to emit electrons in the floating gate to the substrate by a tunnel current. In addition, a reading operation is conducted by applying a predetermined voltage on the word line and one of the bit lines to detect the differences in threshold voltages caused by whether electrons are injected in the floating gate through a cell transistor carrying or not carrying the current.
First, in the conventional manufacturing method described above, the respective first and second floating gates and the respective first and second word lines have to be formed separately so that the number of steps are increased to rise manufacturing costs. Furthermore, a problem is raised that the memory cell characteristics constructed of the first word line are different from those of the second word line because of their different structures.
Secondly, in the conventional manufacturing method, resulting from line width differences between the first and second word lines, a problem is raised that the memory cell characteristics of the memory cell constructed of the first word lines are different from those of the second word lines. In this case, a problem is raised that the distance between the first word lines must be expanded more than the minimum fabrication dimensions thus a memory cell is prevented from being highly dense.
Thirdly, in the conventional manufacturing method, the first and second word lines are formed by masks of a different pattern. Consequently, characteristic failure is generated due to alignment shifts between the masks so that the yield of products or reliability is deteriorated. In particular, a capacitance ratio of the capacitance between the word line as the control gate and the floating gate to the capacitance between the floating gate and the substrate greatly affects the characteristics of the memory cell. However, this capacitance ratio largely depends on the alignment accuracy during the lithography process for patterning the first and second word lines. Accordingly, it is difficult to uniform the characteristics of the memory cells with excellent repeatability.
Fourthly, in the conventional manufacturing method, the planarization is not performed because the second word line is formed over the top of the first word line. Then following metal wiring becomes difficult. Thus, a problem is raised that the yield of products or reliability is deteriorated.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to solve the conventional problems described above and to provide a method for manufacturing a non-volatile semiconductor memory highly integrated, highly reliable, easily manufactured and low-cost and the non-volatile semiconductor memory manufactured thereby.
In order to achieve the object mentioned above, the present invention is a method for manufacturing a non-volatile semiconductor memory cell of a structure provided with a trap gate between a word line serving as a control gate, and a channel region of a substrate, the trap gate is constructed of an insulating layer and capable of trapping a carrier. The trap gate constructed of the insulating layer can change a threshold of a transistor locally because the carriers injected and trapped inside do not move in the gate. As associated with it, the trap gate does not need to be separated between adjacent memory cells. In addition, the insulating layers for electrical isolation need to be formed on and under the trap gate constructed of the insulating layer. However, the gate insulating layer of the three-layers structure can be formed very thin and highly reliably compared with the conventional floating gate structure.
According to a first aspect of the present invention,
Anya Igwe
Smith Matthew
LandOfFree
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