Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-08-04
2010-06-08
Nguyen, Khiem D (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C257SE21540, C257SE29129
Reexamination Certificate
active
07732271
ABSTRACT:
According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.
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Notification of Reasons for Rejection issued by the Japanese Patent Office on Sep. 25, 2009, for Japanese Patent Application No. 2007-005807, and English-language translation thereof.
Hamamoto Takeshi
Nitayama Akihiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nguyen Khiem D
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