Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With decomposition of a precursor
Reexamination Certificate
1999-06-28
2001-07-03
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
With decomposition of a precursor
C117S094000, C117S096000, C438S286000, C438S284000, C438S282000, C438S283000, C438S980000
Reexamination Certificate
active
06254676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to method for manufacturing a metal oxide semiconductor transistor. More particularly, the present invention relates to a method for manufacturing a metal oxide semiconductor transistor having a raised source/drain.
2. Description of Related Art
Progress in semiconductor fabrication technologies has made it possible to fabricate semiconductor devices at the ULST level. However, even though decreasing the size of devices increases the density and operation efficiency of the integrated circuit, such a decrease is still accompanied by a short channel effect, which decreases the device performance. As the size of devices decrease, the major parameters which may affect the electric property of the transistor include: the length of the channel, saturation of speed, resistance of the source/drain region, penetration of electrons, drain induced barrier lowing (DIBL), geometric shape and etc.
When the channel length is shorter than the junction depth of the source/drain, major charges on the channel located below the gate electrode transfer into the junction depletion region of the source/drain and only minor charges transfer into the gate electrode; hence, the threshold voltage is decreased. Conventionally, in order to minimize the variation of the threshold voltage, an extension structure of the source/drain region is formed on the substrate corresponding to the source/drain region of the transistor and an epitaxial layer functioning as a raised source/drain is formed on the source/drain. The high temperature, above about 800 degrees centigrade, at which the epitaxial layer is formed redistributes the dopants previously doped into the extension structure of the source/drain. Therefore, it is hard to control the outline of the shallow junction. Furthermore, the large variation of the threshold voltage and the decreasing of the device reliability are unavoidable.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a metal oxide semiconductor transistor having a raised source/drain, the method comprising the steps of providing a substrate having a source/drain region. A gate oxide layer is then formed on the substrate. Thereafter, a patterned gate electrode is formed on the gate oxide layer. A first spacer is then formed on a sidewall of the gate electrode. The gate oxide layer on the source/drain region, which is located on the opposite sides of the gate electrode, is removed to expose a surface of the substrate. An epitaxial layer is formed on the exposed surface of the substrate and a top surface of the gate electrode. An implantation step is performed on the substrate to form a source/drain extension structure in the substrate while using the gate electrode and the first spacer as a first mask. A second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate to form a heavily doped source/drain while using the gate electrode, the first spacer and the second spacer as a second mask so that the metal oxide semiconductor transistor having a raised source/drain is obtained.
The invention provides a method for manufacturing a metal oxide semiconductor transistor having a raised source/drain, suitable for use on a substrate having a gate electrode, the method comprising the steps of forming a first spacer on a sidewall of the gate electrode and forming an epitaxial layer on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is performed on the substrate to form a source/drain extension structure in the substrate while using the gate electrode and the first spacer as a first mask. A second spacer is formed on the sidewall of the gate electrode and a heavy implantation step is then performed on the substrate to form a heavily doped source/drain while using the gate electrode, the first spacer and the second spacer as a second mask, wherein the characteristic of the invention is that the epitaxial layer is formed before the source/drain extension structure and the heavily doped source/drain.
The invention provides a method for manufacturing a metal oxide semiconductor transistor having a raised source/drain, suitable for use on a substrate having a gate electrode, and a gate oxide layer is formed between the gate electrode and the substrate, the method comprising the steps of forming a first spacer on a sidewall of the gate electrode and forming an epitaxial layer on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is performed on the substrate while using the gate electrode and the first spacer as a first mask. A second spacer is performed on the sidewall of the gate electrode and a heavy implantation step is performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask.
As described in the preferred embodiment of the present invention, the epitaxial layer is formed before the extension structure of the source/drain, Therefore, dopants in the extension structure of the source/drain are prevented from suffering from the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is avoided and the junction outline is controlled more easily than in the prior art.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Chung Hsien-Ta
Huang Chien Chao
Huang Michael W C
Yang Gwo-Shii
Yew Tri-Rung
Kunemund Robert
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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