Method for manufacturing merged DRAM with logic device

Details Method for manufacturing merged DRAM with logic device Method for manufacturing merged DRAM with logic device

2005-02-22

2005-02-22

Pham, Hoai (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000

Reexamination Certificate

active

06858490

ABSTRACT:
In manufacturing merged DRAM with a logic device in a single chip, an oxide layer and a nitride layer are formed on a semiconductor substrate. A hole for exposing the substrate is formed. A silicon epitaxial layer is grown on a portion of the substrate exposed by the hole and an adjacent portion of the nitride layer so that a facet is formed on the nitride layer surface. A thermal oxide layer is grown on the silicon epitaxial layer. The thermal oxide layer is wet etched so that only a growing portion is left on the silicon epitaxial layer. The thermal oxide layer left on the facets of the repeatedly grown silicon epitaxial layer is removed. A gate oxide layer and a gate conductive layer are formed on the resulting substrate. A gate is formed by patterning the gate conductive and oxide layer. A capacitor having a storage node, a dielectric layer, and a plate node is also formed.

REFERENCES:
patent: 5453396 (1995-09-01), Gonzalez et al.
patent: 5843817 (1998-12-01), Lee et al.
patent: 6080632 (2000-06-01), Chao
patent: 20020135029 (2002-09-01), Ping et al.
patent: 20020137269 (2002-09-01), Ping et al.

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