Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-09-12
2006-09-12
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S225700, C714S710000, C714S711000
Reexamination Certificate
active
07106643
ABSTRACT:
Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
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Aoki Masakazu
Etoh Jun
Horiguchi Masashi
Itoh Kiyoo
Antonelli, Terry Stout and Kraus, LLP.
Elms Richard
Hur J. H.
Renesas Technology Corp.
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