Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-04
2001-02-13
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000
Reexamination Certificate
active
06187638
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a memory cell with a increased threshold voltage accuracy, and more particularly to a method for manufacturing a memory cell in a multi-level mask read-only-memory (ROM) with a increased threshold voltage accuracy.
BACKGROUND OF THE INVENTION
Nowadays, the read-only-memory (ROM) has been used in all kinds of digital products because it can save data permanently as the power is turned off, and has an only-read function without needing random-access program code, such as the basic-input-output-system (BIOS) in a personal computer.
Please refer to FIG.
1
(
a
) which is a top view of a structure of a mask ROM with a conventional flat cell. The bit line
10
is disposed along the first direction
101
and is composed of a buried layer structure. A gate conducting layer formed by a tungsten silicide (WSix) layer
111
and a polysilicon layer
112
is formed along the second direction
102
to serve as a word line
11
. Please refer to FIG.
1
(
b
) and FIG.
1
(
c
) which are sectional views of a mask ROM, taken along line A-A′ and line B-B′ respectively. There is a gate oxide layer
13
formed between the substrate
12
and the polysilicon layer
112
, and a photoresist layer
14
is deposited over the mask ROM. The photoresist layer
14
is patterned by photolithography to define the code implantation area
15
and then impurities are doped into the substrate
12
by an ion implantation process for threshold voltage adjustments.
In an ordinary two-level mask ROM for saving binary digital data, the ion implantation process is performed once to distinguish two different threshold voltages (have and haven't been ion implanted in MOS). However, in order to increase the accumulation density in a memory device, the multi-level mask ROM is developed for storing more data in the same device number and same area of MOS. The multi-level mask ROM is made by executing the ion implantation process several times to distinguish the different threshold voltages. Please refer to FIG.
1
(
b
) and FIG.
1
(
c
). By implanting different ion concentration in different code implantation areas, different areas with different threshold voltages are formed. For example, a three-level mask ROM, formed by two times of ion implantation process, has three different areas with three different implantation concentration. Thus, the multi-level logic in a memory cell can fully utilize the device area and save more data without increasing the device number.
However, in conventional processes, ions must be implanted through a thick gate conducting layer
11
which is formed by a WSix layer
111
and a polysilicon layer
112
. The thickness of the WSix layer is ranged from 1000 Å to 1500 Å and so is the polysilicon layer. Therefore, high energy is needed for doping impurities into the substrate
12
. The more the energy is needed to penetrate the gate conducting layer, the more serious the ion scattering effect and the ion concentration variation will be. This serious ion concentration variation makes the threshold voltage of the ion implantation area imprecise. The threshold voltage distribution is in the form of Guass distribution as shown in FIG.
2
. The ion scattering effect causes the threshold voltage overlap. In a multi-level mask ROM, the problem of the overlap is especially serious. To avoid the overlap, the spaces between each threshold voltage should be increased but the number of the threshold voltage will be limited. In other words, the multi-level mask ROM can not save too many data by the applicant. The present invention is tried to deal with the above situation encountered by the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for manufacturing a memory cell, wherein the memory cell with a increased threshold voltage accuracy, has a substrate forming thereon a plurality of first conducting lines in a first direction forming thereon a plurality of second conducting lines in a second direction.
According to the present invention, first of all, a photoresist layer is formed over the first and the second conducting lines. Subsequently, a window is formed on the photoresist layer to expose a portion of the second conducting lines, and the portion of the second conducting lines in the window is thinned. Thereafter, impurities are doped into the substrate between two of the first conducting lines to form the memory cell.
Conventionally, the conducting layer is thick and the doping energy has to be high. Because the high energy can cause a serious ion scattering effect, the threshold voltage is easy to overlap. This problem will make the threshold voltage imprecise. In the present invention, the conducting layer is thinned. Therefore, the energy for doping impurities and the ion scattering effect are lowered to obtain a high threshold voltage accuracy.
In accordance with one aspect of the present invention, before the photoresist layer is formed, the method further includes the steps of forming an dielectric layer over the first and the second conducting lines, and removing a portion of the dielectric layer to expose the second conducting lines.
In an embodiment of the present invention, the dielectric layer is formed by a high density plasma chemical vapor deposition (HDPCVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. The portion of the dielectric layer is removed by an etch back process or a chemical mechanical polishing (CMP) process and the portion of the second conducting lines are thinned by a reactive ion etching.
REFERENCES:
patent: 5514610 (1996-05-01), Wann et al.
patent: 5545580 (1996-08-01), Sheng et al.
patent: 5576236 (1996-11-01), Chang et al.
patent: 5585297 (1996-12-01), Sheng et al.
Bowers Charles
Chen Jack
Rosenberg , Klein & Lee
Winbond Electronic Corp.
LandOfFree
Method for manufacturing memory cell with increased... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing memory cell with increased..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing memory cell with increased... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2589375