Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2000-06-12
2002-03-19
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S311000, C438S327000
Reexamination Certificate
active
06358786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a bipolar mode field effect transistor(BMFET) technique, and more particularly to a lateral BMEFT formed on a silicon-on-insulator (SOI) substrate and a method for manufacturing the same.
2. Description of the Related Art
A BMFET, as a kind of short channel junction field effect transistor(JEFT), improves the current capability thereof through a conductivity modulation of a drift region under a forward biasing of the gate junction. The BMFET is very promising switching device for high-frequency and high-voltage applications, owing to the low forward voltage drop and the high switching speed.
FIG. 1
shows a sectional view of a vertical BMFET, separate element. On a N+ substrate
10
of a drain region is formed a N−drift region
11
of epitaxial layer. In a part of the drift region
11
are formed P+ gate regions
12
and in another part of the drift region
11
is formed N+ source region
13
surrounded by P+gate regions
12
. A drain electrode
17
, a gate electrode
15
and a source electrode
16
are respectively disposed on the drain region
10
, the gate regions
12
and the source region
16
. Between the gate electrodes
15
and the source electrode
16
are disposed insulating layers
14
.
The important feature of the BMFET cell geometry is the channel width between two gate regions under N+ source region. In the normally-off BMFET, a built-in voltage of the junction between P+ gate region
15
and N− drift region
12
can deplete the channel region with width “c” and also create a potential barrier into the channel sufficiently enough to prevent a large electron emission from the source region to the drain region.
In the normally-on BMFET, the conductivity modulation of the drift region
11
with high resistivity occurs by the hole injection under the forward gate-source bias. Accordingly, very low resistance and higher current gain can be obtained.
As one method for apply the vertical BMFET having such an electrical characteristic to an integrated chip, on an epitaxial substrate the lateral BMFET is formed. However, in that case, the parasitic bipolar junction transistor(BJT) caused by the vertical P/N junction is generated and thus the power consumption is increased. Therefore, it has required that a technique which embodies a lateral BMFET suitable for the integrated chip(IC) of power device, with maintaining the electrical characteristic of the conventional vertical BMFET.
On the other hand, a SOI device, recently used widely in the power IC device, the junction capacitance between the substrate and the source/drain regions is almost not occurred because of an insulation region formed on the substrate and thus fast switching speed is possible. Also, since the leakage current into the substrate is suppressed, the SOI power IC device can used under high temperature. Accordingly, the system using SOI substrate for the power IC device has been studied, and there is, as such power IC device, a MOS gate lateral power device like LIGBT(Lateral Insulated Gate Bipolar Transistor), LMCT(Lateral MOS-Controlled Thyristor) and LDMOS (Lateral DMOS). The LDMOS has higher on-resistance than the bipolar device because of the electrons of the majority carrier, so the large power is consumed. However, the LDMOS has fast switching speed. The LIGBT or LMCT has higher current capability and lower on-resistance but the switching speed is rather low owing to the recombination of hole being a minority carrier. That is, although the vertical BMEFT has good electrical characteristic, in case where the BMFET is manufactured for IC the parasitic BJT current path is generated owing to the P/N junction. And, the MOS gate lateral power device using SOI substrate has large on-resistance or low switching speed.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to realize a lateral BMFET suitable for an IC.
In a view of the present invention, a lateral SOI BMFET has a substrate having an N type or P type, a buried insulation layer formed on the substrate and a drift region of the first conductivity formed on the buried insulation layer. In the drift region, a gate region of the second conductivity is disposed over and from the buried insulation layer separated by the first distance. Also, on the buried insulation layer, are disposed a source region of the first conductivity contacting with the gate region and a drain region of the first conductivity opposite to the source region, the drain region separated from the gate region by a selected distance. A source electrode, a gate electrode and a drain electrode are respectively disposed on the side of the source region, on the gate region and the on the drain region. The gate region comprises a plurality of cells arranged parallel to an extension of the source region, each cell separated from adjacent cell by a second distance. Here, the first distance is a channel depth and the second distance is a channel width. The first conductivity is N type and the second conductivity is P type.
In another view of the present invention, a buried insulation layer is formed on a substrate with P type or N type. A drift region of the first conductivity is formed on the buried insulation layer and a trench is made at a part of the buried insulation layer, exposing the buried insulation layer. Then, a gate region of the second conductivity is formed separately from the buried insulation layer by a first distance, at a portion separated from the trench among the drift region. A source region of the first conductivity is formed between the gate region and the trench and at the same time a drain region of the first conductivity opposite to the source region is formed separately from the gate region by a selected distance. The gate region comprises a plurality of cells arranged parallel to an extension of the source region, each cell separated from adjacent cell by a second distance. Here, the first distance is a channel depth and the second distance is a channel width. The first conductivity is N type and the second conductivity is P type. Also, after forming the drain region, an insulation layer is formed on the resultant in which the source region and the drain region are formed and then the insulation layer in the trench and on the gate region and the drain region is removed. Thereafter, the trench is filled with metal, forming a source electrode, and a gate electrode and a drain electrode are formed on the gate region and the drain region.
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patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5510632 (1996-04-01), Brown et al.
patent: 9724282 (1997-05-01), None
Chaudhari Chandra
Hynix / Semiconductor Inc.
Selitto Behr & Kim
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