Method for manufacturing junction semiconductor device

Details Method for manufacturing junction semiconductor device Method for manufacturing junction semiconductor device

2006-03-23

2009-06-09

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S146000, C438S175000, C438S188000, C257S213000, C257S288000, C257S347000, C257S352000, C257SE29233, C257SE29270, C257SE29243

Reexamination Certificate

active

07544552

ABSTRACT:
A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

REFERENCES:
patent: 4738935 (1988-04-01), Shimbo et al.
patent: 5541426 (1996-07-01), Abe et al.
patent: 5554561 (1996-09-01), Plumton et al.
patent: 5705830 (1998-01-01), Siergiej et al.
patent: 6917054 (2005-07-01), Onose et al.
patent: 7449734 (2008-11-01), Nonaka et al.
patent: 2004/0135178 (2004-07-01), Onose et al.
2002 Report on the Results of Research, New Energy and Industrial Technology Development Organization, Development of Ultra Low Loss Power Devices Technology, and Device Design Technology, Research and Development Association for Future Electron Devices.
J. H. Zhao et al., 6A, 1kV 4H-SIC Normally-off Trenched-and-Implanted Vertical JFETs, Materials Science Forum, 2004, 1213-1216, 457-460, Trans Tech Publications, Switzerland.
Takahashi Shinohe et al., 600V5A 4H-SiC with Low RonS of 13mΩcm2, Proceedings of the Symposium on Static Induction Devices, 2002, 41-45, 17.

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