Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-01-11
2011-01-11
Nhu, David (Department: 2895)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S680000, C438S700000, C438S931000, C257SE21170, C257SE21077, C257SE21115, C257SE21129, C257SE21218, C257SE21229, C257SE21248, C257SE21319
Reexamination Certificate
active
07867836
ABSTRACT:
A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 4422089 (1983-12-01), Vaes et al.
patent: 4626879 (1986-12-01), Colak
patent: 5541426 (1996-07-01), Abe et al.
patent: 7449734 (2008-11-01), Nonaka et al.
patent: 2004/0135178 (2004-07-01), Onose et al.
patent: 2005/0029557 (2005-02-01), Hatakeyama et al.
2002 Report on the Results of Research, New Energy and Industrial Technology Development Organization, Development of Ultra Low Loss Power Devices Technology, and Device Design Technology, Research and Development Association for Future Electron Devices.
J. H. Zhao et al., 6A, 1kV 4H-SIC Normally-off Trenched-and-Implanted Vertical JFETs, Materials Science Forum, 2004, 1213-1216, 457-460, Trans Tech Publications, Switzerland.
Takahashi Shinohe et al., 600V5A 4H-SIC with Low RonS of 13mΩcm2, Proceedings of the Symposium on Static Induction Devices, 2002, 41-45, 17.
Hashimoto Hideki
Iwanaga Kensuke
Nonaka Ken-ichi
Saito Yoshimitsu
Yokoyama Seiichi
Birch & Stewart Kolasch & Birch, LLP
Honda Motor Co. Ltd.
Nhu David
LandOfFree
Method for manufacturing junction semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing junction semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing junction semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2725899