Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-22
2001-08-07
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000, C438S594000
Reexamination Certificate
active
06271090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more particularly to a method for manufacturing a flash memory device with dual floating gates and two bits per cell.
2. Description of the Related Art
In the last decade, semiconductor memories have been the fastest growing segment of the semiconductor industry, with the large increase due to the rapid growth of digital electronics market with multiplying applications. Moreover, flash electrically programmable read only memories devices (EPROM) are being produced in larger quantities. Lately, high-density flash memory has been expected to share a certain part of the large computer external storage device market. One of the goals in the fabrication of flash EPROM is the production of a memory circuit that is capable of storing a maximum amount of information using a minimum amount of semiconductor surface area. However, photolithographic limits imposed by conventional semiconductor processing technology impede the achievement of this goal. Thus, the inability to pattern and etch semiconductor features closed together prevents a memory cell from occupying a smaller portion of a semiconductor's surface. Another goal of flash EPROM manufacturing is use of a simple cheap high yielding process. Many previous methods to reduce device size add too much complexity and cost.
Flash EPROM frequently uses a floating gate avalanche injection metal oxide semiconductor (FAMOS) structure to store information. Floating gate dimensions in a FAMOS memory cell are conventionally established with reference to minimum photolithographic limits and therefore produce undesirable large memory cells. A conventional configuration for an EPROM device is the stacked gate structure as shown in FIG.
1
. Source
12
and Drain
14
regions are formed in substrate
10
. The floating gate
16
overlies the channel region, the area between the source and drain. The control gate
18
overlays the floating gate
16
. An insulating structure
20
insulates the substrate, floating gate and control gate. The minimum size of the conventional stacked gate structure is determined by the photolithographic limits which determine the floating gate, control gate, source and drain widths.
In view of the drawbacks of the prior method used to manufacture flash memory devices set forth, it is very necessary to provide a method that can overcome the photolithography limits, meanwhile, reduce the cost and complexity amid the process of manufacturing the flash memory devices. It is towards those goals that the present invention is specifically directed.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for manufacturing flash EPROM devices with dual floating gates and two bits per cell, and overcoming the photolithographic limits of imposed by conventional semiconductor processing technology to manufacture smaller flash EPROM devices.
It is another object of this invention to overcome the photolithographic limits and increase the integration of the flash memory circuit by using the technique of self-align etching of the dual floating gates.
It is a further object of this invention to reduce the cost of manufacturing the flash memory circuit by omitting the photolithography process of manufacturing the floating gates.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a self-align etching technique to form dual floating gates by using dual spacers as masks. First of all, a semiconductor substrate comprising a first insulating layer formed conformally thereon, and a first conductive layer formed over the first insulating layer is provided. Then a second insulating layer is formed over the first conductive layer. A central region pattern is next transferred into the second insulating layer to form a trench and expose the first conductive layer. A dielectric layer is then deposited over the semiconductor substrate. The dielectric layer is anisotropically etched to form dual spacers separately laterally adjacent sidewalls of said trench and expose the second insulating layer. After removing the second insulating layer, the first conductive layer is etched by using the dual spacers as masks to form dual floating gates and expose the first insulating layer. After removing the dual spacers, two doped regions separately located on two sides of said dual floating gates are then formed by using a photolithography and an ion implantation processes. After thickening the first insulating layer, a composite layer, a second conductive layer and a third insulating layer is formed over the semiconductor substrate sequentially.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5143860 (1992-09-01), Mitchell et al.
patent: 5492846 (1996-02-01), Hara
patent: 5646059 (1997-07-01), Sheu et al.
patent: 5714412 (1998-02-01), Liang et al.
patent: 6197637 (2001-03-01), Hsu et al.
Chen Hsin-Huei
Chiou Frank
Huang Chong-Jen
Liu Lenvis
Wang Tony
Booth Richard
Macronix International Co. Ltd.
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