Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-18
2004-07-06
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000
Reexamination Certificate
active
06759299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to formation of a peripheral region when a flash memory device is manufactured, and more particularly to, a method of manufacturing a flash memory device by which a low-voltage transistor is formed to have a DDD junction structure when a high-voltage transistor in a peripheral region of the flash memory device is formed.
2. Description of the Prior Art
Generally, the flash memory device is divided into a cell region and a peripheral region. The peripheral region is divided into a HV (high voltage) region in which a high-voltage transistor is formed, and a LV (low voltage) region in which a low-voltage transistor is formed. The gate oxide films each formed at the cell region and the peripheral region have different thickness depending on the characteristic of each of the regions. For example, a tunnel oxide film is formed as the gate oxide film of the cell region, the gate oxide film for high voltage is formed at the HV region of the peripheral region, and the gate oxide film for low voltage is formed at the LV region.
After the gates of the high-voltage transistor and the low-voltage transistor are formed, a junction is formed. A method of forming the low-voltage transistor and the high-voltage transistor in the peripheral region of the flash memory device will be below described by reference to FIG.
1
A and FIG.
1
B.
In FIG.
1
A and FIG. B, MC indicates a main cell section, LV indicates a region where the low-voltage transistor is formed and HV indicates a region where the high-voltage transistor is formed. Also, a reference numeral ‘
10
’ represents a substrate and ‘
12
’ represents the gates of each the regions.
Referring first to
FIG. 1A
, a LDD (lightly doped drain) junction
16
of the low-voltage transistor is formed. In other words, only a portion where the low-voltage transistor is formed is opened using a mask
14
for a low voltage. An implantation process is then performed to form the LDD junction
16
.
By reference to
FIG. 1B
, a junction of the low-voltage transistor is formed. Only a portion where the high-voltage transistor is formed is then opened using a mask
18
for a high voltage. Next, an ion implantation process is performed to form a DDD (double doped drain) junction
20
.
As the semiconductor devices become increasingly fine, the size of the peripheral region is necessarily reduced. Accordingly, there are several problems in the low-voltage transistor. For example, the performance of the transistor is degraded due to hot carrier injection. Thus, erroneous operation occurs in the transistor, which degrades the device characteristics. As described above, as the junction of the low-voltage transistor is separately formed, there are problems that the number of the process step is increased and the cost is thus increased. In case where the low-voltage transistor and the high-voltage transistor are separately formed, the device characteristics depending on the hot carrier injection will be described by reference to FIG.
2
.
FIG. 2
is a graph for explaining the lifetime of the transistor when the low-voltage transistor is formed by the prior art.
As can be seen from
FIG. 2
, the lifetime of the low-voltage transistor formed to have the LDD junction when Vd is 3.6V is 431 hours due to the hot carrier injection. This does not satisfy a standard of 2000 hours.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a flash memory device by which a low-voltage transistor is formed to have a DDD structure same to a high-voltage transistor when a peripheral region is formed in the manufacture process of the flash memory device.
The above object of the present invention is achieved by a method of manufacturing a flash memory device comprising the steps of preparing a semiconductor substrate divided into a main cell region and a peripheral region, wherein the peripheral region is divided into a high-voltage region in which a high-voltage transistor will be formed and a low-voltage region in which a low-voltage transistor will be formed according to the present invention, forming a device isolation film in the semiconductor substrate, performing a ion implantation process for forming well and a ion implantation process for controlling threshold voltage for the substrate, thus forming a well region, forming gates, forming a mask in the main cell region so that the peripheral region is opened and then performing an ion implantation process for the high-voltage region and the low-voltage region, thus forming a DDD low-concentration junction regions, forming spacers at sidewalls of the gates in the high-voltage region and the low-voltage region, and forming a mask in the main cell region so that the peripheral region is opened and then performing an ion plantation process for the high-voltage region and the low-voltage region, thus forming a DDD high-concentration junction regions.
REFERENCES:
patent: 4630356 (1986-12-01), Christie et al.
patent: 6159795 (2000-12-01), Higashitani et al.
patent: 6420222 (2002-07-01), Watanabe
patent: 2003/0003660 (2003-01-01), Hsu et al.
patent: 2003/0008458 (2003-01-01), Hashimoto et al.
Ahn Jung Ryul
Jung Sung Mun
Lee Young Bok
Booth Richard A.
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
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