Method for manufacturing field effect transistor

Details Method for manufacturing field effect transistor Method for manufacturing field effect transistor

2007-08-21

2007-08-21

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S530000, C257SE21453

Reexamination Certificate

active

11225187

ABSTRACT:
The manufacturing stability can be improved while effectively inhibiting the short-channel effect in the transistor according to the present invention. A halo impurity having a conductivity type opposite to a first conductivity type of a first impurity is ion-implanted into the silicon substrate101, and thereafter the first impurity having the first conductivity type, is ion-implanted and then a flash lamp annealing is conducted to form a p-type halo region113and a n-type extension region111. Then, the second impurity having the first conductivity type is ion-implanted into the silicon substrate101, and then a flash lamp annealing is conducted to form a n-type source/drain region109. Then, the impurity contained in the silicon substrate101is activated via spike RTA.

REFERENCES:
patent: 6797593 (2004-09-01), Chakravarthi et al.
patent: 2004/0053457 (2004-03-01), Sohn
patent: 2004/0157469 (2004-08-01), Ito
patent: 2004-063574 (2004-02-01), None
patent: 2004-253446 (2004-09-01), None
Akira Mineji et al., “Improvements of Electrical Properties with Reduced Transient-Enhanced-Diffusion for 65nm-node CMOS Technology using Flash Lamp Annealing”, Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, Tokyo, pp. 412-413, Sep. 15, 2004.

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