Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-10
2004-10-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06803284
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to manufacturing non-volatile memory, having small critical dimensions, particularly suited as embedded memory on complex integrated circuits.
2. Description of Related Art
As the size of components on integrated circuits shrinks, the degree of integration of functional units on a single chip is increasing. Thus, many chips are being designed which include embedded nonvolatile memory along with logical components, such as memory controllers, general-purpose processors, input/output interface logic, dedicated logic, digital signal processors, and a wide variety of other functional units.
The small dimensions of components on complex integrated circuits present design difficulties. For example, the small width of diffusion conductors increases the resistance of the conductors. Thus, it is known to use technology known as salicide, or other technology, to form a highly conductive layer on the surface of the diffusion conductors to decrease the resistance. According to the well-known salicide process, a silicide such as tungsten silicide is formed on the surface of the diffusion conductors using a self-aligned deposition process. However, application of the salicide process is incompatible with some processes for forming high-density memory cells.
For example, one step used in the salicide process is sidewall formation. The sidewalls are used for masks in the self-alignment step. Sidewall formation includes an etch step, often a plasma based etch, by which the layer of oxide, or other sidewall material, is etched back to the underlying dielectric layer in regions over diffusion conductors. This etch back step can damage the surface of the silicon substrate, resulting in a damaged surface across which a leakage path can be formed. This leakage path can be damaging particularly in high-density memory arrays, causing soft breakdown of the memory.
Another problem that arises because of the high-density of modern technologies is the so-called short channel effect. Because the channel lengths in small dimension transistors are so small, diffusion of dopants implanted to form source and drain regions due to oxidation and thermal processes that occur after the implant can undesirably shorten the channels of the transistors. These effects occur because of so-called thermally enhanced diffusion TED and so-called oxidation enhanced diffusion OED.
It is desirable, therefore, to provide a manufacturing process suitable for combined manufacturing of high-density nonvolatile memory with advanced logic peripheral circuits, which reduces or minimizes effects of small dimension components, such as the short channel effect, the soft breakdown effect due to oxide damage, the high resistance of narrow diffusion conductors, and the like.
SUMMARY OF THE INVENTION
The present invention provides a process using two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. An embodiment of the present invention provides a method for manufacturing an integrated circuit on the substrate, including nonvolatile memory in an array portion of the substrate and other circuitry in a non-array portion of the substrate. The method includes integrated circuit manufacturing steps comprising:
forming gate dielectric layers in the array portion and in the non-array portion of the substrate;
covering the gate dielectric layer with a first layer of polysilicon in the array portion and in the non-array portion of the substrate;
covering the first layer of polysilicon with a layer of silicon nitride in the array portion and in the non-array portion of the substrate;
patterning lines in a wordline direction in the array portion, and etching said layer of silicon nitride and said first layer of polysilicon to form line structures;
patterning lines orthogonal to the wordline direction in the array portion over said line structures, and etching said line structures to form gate electrode structures, the gate electrode structures including remaining portions of said first polysilicon layer and said silicon nitride layer;
implanting dopants into the substrate through the gate dielectric layer between the lines orthogonal to the wordline direction;
removing said lines orthogonal to the wordline direction;
depositing a dielectric material among the gate electrode structures to fill gaps among the gate structures;
planarizing the array portion and the non-array portion to a level exposing said silicon nitride layer and said dielectric material in the gaps among the gate electrode structures;
removing said layer of silicon nitride from said non-array portion and from said gate structures, leaving the remaining portions of said first layer of polysilicon and said dielectric material filling the gaps among the gate electrode structures;
covering the remaining portions of said first layer of polysilicon and said dielectric material filling the gaps among the gate electrode structures with a second layer of polysilicon material;
patterning wordlines in the array portion over said gate electrode structures, and transistor gate structures in said non-array portion, and etching the remaining portions of said first layer of polysilicon and said second layer of polysilicon according to the patterning, to form wordlines in the array portion and transistor gate structures in the non-array portion;
implanting dopants to form source and drain regions in the non-array portion;
forming self aligned silicide in source and drain regions in the non-array portion;
applying a dielectric layer over the array portion and the non-array portion; and
applying patterned metallization over the dielectric layer.
The first polysilicon layer as deposited in various embodiments has a thickness of around 300 Angstroms, and preferably in a range of about 200 to about 450 Angstroms. The nitride layer as deposited in various embodiments has a thickness of around 300 Angstroms, and preferably in a range of about 200 to about 450 Angstroms. The second polysilicon layer as deposited in various embodiments has a thickness of around 1500 Angstroms, and preferably in a range of about 1300 to about 1600 Angstroms.
Embodiments of the invention also include so-called lightly doped drain LDD processes to improve transistor performance, particularly in the peripheral circuitry. Thus, in embodiments including the LDD processes, the method of implanting dopants to form source and drain regions in the non-array portion includes implanting a first dopant aligned with the transistor gate structures, forming sidewall spacers on the transistor gate structures, and implanting a second dopant aligned with the sidewall spacers. Silicide is formed, in these LDD embodiments, using processes self-aligned with the sidewall spacers. In some embodiments, the sidewall spacers are made using silicon nitride, or other material that is different than the material of the deposited dielectric and gate dielectric layer, so that a selective etch process can be used during formation of the sidewall spacers, to minimize damage of the underlying gate dielectric layer.
Embodiments of the invention use chemical vapor deposition to deposit the dielectric material among the gate structures to fill gaps among the gate structures. Preferably, plasma enhanced chemical vapor deposition, or another low-temperature chemical vapor deposition process, is used. For example, deposition processes in which the deposition temperature is less than 650 degrees Celsius are preferable.
The step of planarizing is accomplished using chemical mechanical polishing in embodiments of the manufacturing method, to further reduce the thermal “budget” on the manufacturing process.
The manufacturing process outlined above is applicable to mask ROM embedded memory arrays, as well as to embedded, electrically programmable and erasable memory arrays using so-called SONOS memory cells, which have gate dielectrics based on a composite layer, including a
Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Hoang Quoc
Macronix International Co. Ltd.
Nelms David
LandOfFree
Method for manufacturing embedded non-volatile memory with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing embedded non-volatile memory with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing embedded non-volatile memory with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3287970