Method for manufacturing embedded dynamic random access memory

Details Method for manufacturing embedded dynamic random access memory Method for manufacturing embedded dynamic random access memory

2000-05-02

2002-10-29

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000

Reexamination Certificate

active

06472265

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89104239, filed Mar. 9, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor. More particularly, the present invention relates to a method for manufacturing an embedded dynamic random access memory (DRAM).
2. Description of Related Art
In order to decrease the semiconductor manufacturing cost and simplify the fabrication procedures, a method for putting memory cell and logic circuit devices together on a semiconductor chip is developed. The structure integrating a logical device and a memory device on the same wafer is called system on chip (SOC).
Typically, an embedded DRAM comprises a memory device region and a logic circuit region. The memory devices and the logic devices are together formed on the same wafer. The benefits of the embedded DRAM include high yield, short cycle time and low manufacturing cost. However, the specificity requirements of the memory devices and the logic devices are different from each other, so that the process procedures for manufacturing the embedded DRAM must be modified to fit those requirements. Taking the logic device as an example, the logic device requires relatively high operation rate. On the other hand, the refreshing time of memory capacitors must be as long as possible. Therefore, the memory transistors must be fabricated in a manner slightly different from the logic devices.
FIG. 1
is a schematic cross-sectional view showing a portion of a conventional embedded DRAM with both logic devices and memory cell transistors therein.
As shown in
FIG. 1
, a substrate
100
that includes a logic circuit region
102
and a memory cell region
104
is provided. A DRAM is formed in the memory cell region
104
, wherein the DRAM includes three transistors
108
,
110
,
112
and a capacitor (not shown). A transistor
106
is formed in the logic circuit region
102
. The gate conductors of the transistors
106
,
108
,
110
and
112
consist of polysilicon layer, tungsten silicide layer and silicon nitride layer from the bottom to the top of the gate conductors in sequence.
When integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. However, source/drain region resistance in metal oxide semiconductor (MOS) transistors simultaneously increases, and the polysilicon electrodes that form the MOS gates and wiring lines within semiconductor devices introduce undesirable resistance. In order to reduce resistance and RC delay time to improve the operating speed of a device, a self-aligned silicide (salicide) process is employed, and to reduce the sheet resistance of the source/drain regions in order to preserve the integrity of shallow junctions between the metal layer and the MOS transistor. Therefore, a response time or an operating speed of the whole device is increased by reducing the gate resistance and the junction resistance.
Traditionally, a buffer layer is conformal formed over the substrate
100
. Then, a mask layer is formed on the buffer layer in the memory cell region
104
to expose the buffer layer in the logic circuit region
102
. Next, the buffer layer in the logic circuit region
102
is removed to expose a portion of the substrate
100
. Subsequently, a self-aligned silicide process is performed to form a silicide layer
118
on the surface of source/drain regions
114
in the logic circuit region
102
.
In order for the memory cell device to be reliable, and the logic circuit device to have high performance. To increase the speed of operation of the transistor
106
in the logic circuit region
102
, self-aligned silicide layers
118
are formed on the source/drain regions
114
of the transistor
106
. However, in order to extend the refreshing period of DRAM in the memory cell region
104
, resistance at the junction between the capacitor in DRAM and the source/drain region
116
of the transistors
108
,
110
and
112
must be increased. Consequently, a silicide layer is usually not formed over the source/drain regions of the transistors
108
,
110
and
112
in the memory cell region
104
to avoid junction leakage between the capacitor in DRAM and the source/drain region
116
of the transistors
108
,
110
and
112
.
Hence, in general, before self-aligned silicide layers are formed on the source/drain regions of the transistor in the logic circuit region, it is necessary to additionally form a barrier layer such as a silicon nitride layer over the wafer. Then, a mask is used to separate the Logic region and DRAM region. The barrier layer in the logic circuit region is removed, and then a silicide layer is formed in the logic circuit region. Finally, the mask and the barrier layer are removed after the self-aligned silicide process is complete.
After the mask layer and the barrier layer are removed, poly plug and tungsten plug are respectively formed on the substrate
100
in the memory cell region
104
and the logic circuit region
102
. The poly plug and tungsten plug are connected with the source/drain region
116
in the memory cell region
104
and the source/drain regions
114
in the logic circuit region
102
, respectively.
Because the doped concentration of the source/drain regions in DRAM is low, it cannot generate good ohmic contact if tungsten plug is used. Therefore, doped poly plug is generally used to contact with the source/drain regions in the DRAM. However, contact resistance formed thereon is slightly higher, lower resistance can be formed if tungsten plugs are used both in DRAM and logic circuit region. Consequently, the contact resistance in the DRAM is reduced and the manufacturing steps are simplified.
Ideally, silicide layers are formed over the source/drain regions
116
of transistors in the memory cell region as well as the source/drain regions
114
of transistors in the logic device region, wherein the silicide layer formed on the source/drain regions
116
of transistors in the memory cell region does not induce junction leakage increase. However, such a configuration can hardly be achieved through a conventional process.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing an embedded DRAM. It can form silicide layers in memory cell region and logic circuit region that does not induce junction leakage increase and can use W-plug in both memory cell region and logic circuit region.
The invention provides a method of manufacturing an embedded DRAM. A substrate having a memory cell region and a logic circuit region is provided. A capacitor in the memory cell region can be a deep trench capacitor formed within the substrate or a stack capacitor formed over the substrate after MOS transistors are formed. However, the capacitor process is not described herein since it is not strongly related to the scope of the present invention.
A plurality of isolation structures are formed in the substrate to define active regions, and then a gate dielectric is formed on the substrate. Next, a doped polysilicon layer is formed over the substrate, wherein the polysilicon layer can be doped by either in-situ n
+
type ions doping or n
+
/p
+
dual implantation. Subsequently, a silicide layer and a cap layer are formed on the doped polysilicon layer in sequence.
The cap layer, the silicide layer, the doped polysilicon layer and the gate dielectric are defined by reactive ion etch (RIE) to form a plurality of gate conductors on the substrate in the memory cell region and the logic circuit region. After the gate conductors are formed, a thermal oxidation step is performed to recover the gate dielectric damage due to reactive ion etch. Then, LDD implant is followed if necessary.
A spacer is formed on a sidewall of each gate conductors. Then, after surface clean, an undoped Si selective epitaxy is formed selectively on the exposed area of the substrate surface to service as source/drain regions in the logic circuit reg

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