Method for manufacturing dual work function gate electrodes...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S517000, C438S530000, C438S532000, C438S592000, C438S655000

Reexamination Certificate

active

10897846

ABSTRACT:
The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer135aover which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.

REFERENCES:
patent: 5679585 (1997-10-01), Gardner et al.
patent: 6174775 (2001-01-01), Liaw
patent: 6204103 (2001-03-01), Bai et al.
patent: 6784060 (2004-08-01), Ryoo
patent: 6835639 (2004-12-01), Rotondaro et al.
patent: 6841441 (2005-01-01), Ang et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 6864163 (2005-03-01), Yu et al.
patent: 6925008 (2005-08-01), Ichige et al.
patent: 7045456 (2006-05-01), Murto et al.
patent: 7148546 (2006-12-01), Visokay et al.
patent: 2003/0039146 (2003-02-01), Choi
patent: 2003/0109121 (2003-06-01), Rotondaro
patent: 2003/0111686 (2003-06-01), Nowak
patent: 2004/0002185 (2004-01-01), Takahashi
patent: 2004/0238859 (2004-12-01), Polishchuk et al.
patent: 2004/0266113 (2004-12-01), Kirkpatrick et al.
patent: 2004/0266153 (2004-12-01), Hu
patent: 2005/0258468 (2005-11-01), Colombo et al.
patent: 2005/0258500 (2005-11-01), Colombo et al.
patent: 2006/0011996 (2006-01-01), Wu et al.
B. Cheng, et al.; “Metal Gates for Advanced Sub-80 nm SOI CMOS Technology”; 2001 IEEE Intl. SOI Conference; pp. 91-92.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for manufacturing dual work function gate electrodes... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing dual work function gate electrodes..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing dual work function gate electrodes... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3918339

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.