Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-07
2002-06-04
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S591000, C438S981000
Reexamination Certificate
active
06399443
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the manufacturing of dual voltage flash integrated circuits and more particularly to a method in which the mask steps may be reduced and conventional processing used.
BACKGROUND ART
Flash electrically-eraseable programmable and read-only memories (flash EEPROMs) are a class of non-volatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. Flash EEPROMs are read/programmed byte-by-byte or word-by-word, and are erased globally (full chip erase) or partially by a particular portion of the overall array (sector erase). These integrated circuits generally require dual voltages for operation and have peripheral semiconductor devices along with the flash memory cell which use these dual voltages.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip) having a heavily doped drain region and a source region embedded in the semiconductor substrate. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded in the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multilayer structure, commonly referred to as a “stacked gate” structure by which the charge indicative of the state of the flash EEPROM is controlled.
In the past, in manufacturing a dual voltage flash EEPROM, after active and floating gate polysilicon areas are formed, alternating layers of oxide-nitride-oxide (ONO) dielectric material was thermally grown on the polysilicon and the silicon substrate. A photoresist mask (mask) was then introduced to selectively allow removal of the top oxide and nitride layers of the ONO, followed by an oxide stripping etch to remove the bottom oxide of the ONO at the peripheral region of the integrated circuit.
An oxide (for high voltage devices) was thermally grown (a gate oxidation I) after removal of the mask.
Subsequently, a number of masks had to be used for the low voltage (LV) well, field, channel, and voltage threshold (V
t
) implant. A first is used for the LV N-well implant, a second for an LV P-field (Pfld) implant, a third mask for an LV thin gate (first voltage) P-channel V
t
implant, a fourth mask for an LV thick-gate (second voltage) P-channel V
t
implant, a fifth mask for an LV thin-gate (first voltage) N-channel V
t
implant, and a sixth mask for an LV thick-gate (second voltage) N-channel V
t
implant.
A further mask is then introduced for the LV thick gate oxidation creation, and oxide strip is implemented to remove the gate oxidation I at the LV region. A gate oxide then was thermally grown (a gate oxidation II) after removal of the mask. Finally, another mask was used for the LV thin gate oxide creation and a further oxide strip.
Finally, a further polysilicon is deposited and the remaining conventional steps of the manufacturing process for the flash EEPROM are performed.
The above steps are problematic because of the number of masks required and incompatability with individual processes used by different foundries. A solution which would allow for a simplified more universal process has long been sought, but has equally long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gate including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer. This method is simplified over the prior art and uses individual processes which are conventional and well-known to those skilled in the art.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5723355 (1998-03-01), Chang et al.
patent: 5888869 (1999-03-01), Cho et al.
patent: 6184093 (2001-02-01), Sung
patent: 6331492 (2001-12-01), Misium et al.
Chwa Siow Lee
Lin Yung Tao
Chartered Semiconductor Manufacturing LTD
Chaudhari Chandra
Ishimaru Mikio
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