Method for manufacturing DRAM capacitor

Details Method for manufacturing DRAM capacitor Method for manufacturing DRAM capacitor

1999-06-09

2000-10-24

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438595, H01L 218242

Patent

active

061366463

ABSTRACT:
A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bit line contacts, and each bit line contact is connected electrically to one of the first plugs. A cap layer is formed on top of the bit lines and spacers are formed on the sidewalls of the bit lines. The spacers are formed in such a way that they are linked near the bit line contact of every pair of neighboring bit lines. A planarized second insulation layer is formed over the substrate. Using the cap layers, the spacers and the second plugs as stopping points, an etching operation is carried out to form the lower electrode openings of capacitors and node contact openings. A conformal conductive layer that covers the exposed surfaces of the electrode openings and the node contact openings are formed, hence forming the lower electrode of a capacitor. A dielectric layer is formed over the lower electrode, and finally an upper electrode is formed over the dielectric layer to form a complete capacitor.

REFERENCES:
patent: 5763286 (1998-06-01), Figura et al.
patent: 5960294 (1998-09-01), Zahurak et al.
patent: 5981333 (1998-06-01), Parekh et al.

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