Method for manufacturing DRAM capacitor

Details Method for manufacturing DRAM capacitor Method for manufacturing DRAM capacitor

1998-04-03

2000-07-11

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438657, H01L 218242

Patent

active

060872187

ABSTRACT:
A method for manufacturing DRAM capacitor that utilizes a self-aligned etching process for fabricating the lower electrode of a capacitor instead of a conventional photolithographic process whose processing accuracy is dependent upon the resolution of light source used. Using a polysilicon layer as a mask and a silicon nitride layer as an etching stop layer, the self-aligned etching process is carried out to form a rather narrow contact window in the insulating layer. By forming this narrow contact window, proper isolation between a word line and its neighboring conductive layer is ensured. Hence, device reliability is increased.

REFERENCES:
patent: 5741722 (1998-04-01), Lee
patent: 5759895 (1998-06-01), Tseng
patent: 5763306 (1998-06-01), Tsai

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