Method for manufacturing CMOS semiconductor device

Details Method for manufacturing CMOS semiconductor device Method for manufacturing CMOS semiconductor device

1998-03-27

2001-01-09

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S532000

Reexamination Certificate

active

06171897

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a CMOS semiconductor device. More particularly, the present invention relates to a method for manufacturing a CMOS semiconductor device having a p type gate and an n type gate (dual gates) on a single semiconductor substrate.
2. Related Arts
A conventional method for manufacturing a CMOS semiconductor device having dual gates is shown in FIG.
2
(
a
) to FIG.
2
(
c
).
A device isolation region
32
is formed in a silicon substrate
31
. Then, an NMOS transistor formation region
33
which is to become an NMOS region and a PMOS transistor formation region
34
which is to become a PMOS region are formed in the silicon substrate
31
. Next, a gate insulating film
35
is formed on the surface of both the NMOS transistor formation region
33
and the PMOS transistor formation region
34
. Then, a polysilicon film
36
is deposited on the entire surface of the silicon substrate
31
(FIG.
2
(
a
)).
A resist mask
37
a
is formed on the polysilicon film
36
so as to cover the PMOS transistor formation region
34
. Next, n type impurity ions are implanted at a high concentration into the polysilicon film
36
in exposed state to form a high concentration n type polysilicon film
38
on the NMOS transistor formation region
33
(FIG.
2
(
b
)).
The resist mask
37
a
is removed. Then, a resist mask
37
b
is formed on the n type polysilicon film
38
so as to cover the NMOS transistor formation region
33
. Then, p type impurity ions are implanted at a high concentration into the polysilicon film
36
in exposed state to form a high concentration p type polysilicon film
39
on the PMOS transistor formation region
34
(FIG.
2
(
c
)).
The resist mask
37
b
is removed. Next, a thermal-treatment is conducted in order to uniformize the impurity concentration in both of the n type polysilicon film
38
and the p type polysilicon film
39
. A resist film is formed on the entire surface of the silicon substrate Then, a resist mask
37
c
is formed by patterning the resist film. Both the n type polysilicon film
38
and the p type polysilicon film
39
are etched with the resist mask
37
c
used as a mask, whereby an n type gate electrode
40
is formed on the NMOS transistor formation region
33
and a p type gate electrode
41
is formed on the PMOS transistor formation region
34
.
Generally, an etching rate of the high concentration n type polysilicon film
38
and that of the high concentration p type polysilicon film
39
are different. Therefore, if the n type polysilicon film
38
is etched simultaneously with the p type polysilicon film
39
in a step for forming the gate electrodes, the n type polysilicon film
38
having a larger etching rate is completely etched and besides, the silicon substrate
31
of the NMOS transistor formation region
33
is over-etched, thereby causing a rough surface on the substrate as shown in FIG.
3
(
a
). On the other hand, if the p type polysilicon film
39
is etched simultaneously with the n type polysilicon film
38
in a step for forming the gate electrodes, the p type polysilicon film
39
having a smaller etching rate is not fully etched, as shown in FIG.
3
(
b
), thereby causing a problem such as a short-circuit.
The thinner a gate oxide film becomes in accordance with the size reduction of LSI, the bigger the above-mentioned problem becomes. Moreover, this problem can be a cause of extremely decreasing a process precision and reliability of the transistor.
To avoid this problem, a method is considered, which involves conducting an etching of the n type polysilicon film
38
and of the p type polysilicon film
39
separately.
However, in accordance with this method, another alignment process for forming a photo-resist mask is necessary. Accordingly, there arise problems such as lower productivity and higher production costs.
SUMMARY OF THE INVENTION
Thus, the present invention provides a method for manufacturing a CMOS semiconductor device having a first conductivity type MOS transistor including a gate electrode made of a first conductivity type polysilicon film of high impurity concentration and a second conductivity type MOS transistor including a gate electrode made of a second conductivity type polysilicon film of high impurity concentration on a single semiconductor substrate, comprising the steps of:
forming a polysilicon film on the semiconductor substrate;
forming a first resist mask on the polysilicon film so as to cover a second conductivity type MOS transistor formation region, followed by implanting a first conductivity type impurity at a high concentration into the polysilicon film by using the first resist mask;
removing the first resist mask;
forming a second resist mask on the polysilicon film so as to cover a first conductivity type MOS transistor formation region, followed by implanting a second conductivity type impurity at a high concentration into the polysilicon film by using the second resist mask;
etching the second conductivity type polysilicon film by a specific thickness by using the second resist mask;
removing the second resist mask;
thermally treating for uniformizing the impurity concentration in the first conductivity type polysilicon film and the second conductivity type polysilicon film;
forming a third resist mask on the first conductivity type polysilicon film and the second conductivity type polysilicon film; and
etching the first conductivity type polysilicon film and the second conductivity type polysilicon film simultaneously by using the third resist mask thereby forming the gate electrode made of the first conductivity type polysilicon film of high impurity concentration and the gate electrode made of the second conductivity type polysilicon film of high impurity concentration.


REFERENCES:
patent: 4703552 (1987-11-01), Baldi et al.
patent: 5021354 (1991-06-01), Pfiester
patent: 5021356 (1991-06-01), Henderson et al.
patent: 5567642 (1996-10-01), Kim et al.
patent: 7-153847 (1995-06-01), None

Affiliated with

Also associated with

Rating

Method for manufacturing CMOS semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing CMOS semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing CMOS semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2436738