Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-04-26
1999-11-09
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438230, 438231, H01L 218238
Patent
active
059813253
ABSTRACT:
A method of manufacturing a CMOS. A substrate is provided, wherein the substrate has a first conductive-type well, a second conductive-type well, an isolation structure formed therein, a first gate electrode on the second conductive-type well and a second gate electrode on the first conductive-type well. The first conductive-type well and the second conductive-type well are partly isolated from each other by the isolation structure. A first offset spacer is formed on a sidewall of the first and the second gate electrodes and a second offset spacer on a sidewall of the first offset spacer, wherein a portion of the first offset spacer extends on a surface of the substrate and the second offset spacer is on the portion of the first offset spacer. A first LDD region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the second offset spacer. The second offset spacer is removed to expose a portion of the first offset spacer extending on a portion of a surface of the substrate. A second LDD region having the second conductive type is formed in a portion of the first conductive-type well and exposed by the second gate electrode and the first offset spacer under the portion of the first offset spacer extending on a portion of a surface of the substrate. A spacer is formed on a sidewall of the first and the second gate electrodes. A first doped region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the spacer. A second doped region having the second conductive type is formed in a portion of the first conductive-type well exposed by the second gate electrode, the first offset spacer and the spacer.
REFERENCES:
patent: 5759885 (1998-06-01), Son
patent: 5766991 (1998-06-01), Chen
patent: 5851866 (1998-12-01), Son
patent: 5898203 (1999-04-01), Yoshitomi et al.
Bowers Charles
Chen Jack
Huang Jiawei
United Microelectronics Corp.
United Semiconductor Corp.
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