Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-22
2001-10-30
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S649000, C438S393000
Reexamination Certificate
active
06309925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method for manufacturing a capacitor.
2. Description of the Related Art
Most capacitors that are formed in conjunction with other semiconductor devices have a pair of polysilicon electrodes. However, the polysilicon electrodes have some drawbacks including the formation of a depletion region whose thickness may vary. A variable thickness often leads to a variation of capacitance and a degradation of device performance. In the current state of technology, variation in depletion layer thickness often results in an even greater variation in capacitance because the inter-electrode dielectric layer has become thinner due to miniaturization.
FIGS. 1A through 1C
are schematic cross-sectional views showing the progression of manufacturing steps for producing a conventional polysilicon electrode capacitor. Since a transistor is also formed in the peripheral circuit region at the same time, the steps for forming the transistor in the peripheral circuit region are also shown in
FIGS. 1A through 1C
.
As shown in
FIG. 1A
, a semiconductor substrate
100
having a memory cell region
100
a
and a peripheral circuit region
100
b
is provided. The memory cell region
100
a
has a field isolation structure
102
already formed in the substrate
100
. Using chemical vapor deposition and conventional photolithographic techniques, a bottom polysilicon electrode
104
is formed over the field isolation structure
102
. Chemical vapor deposition is conducted again to form a dielectric layer
106
over the bottom polysilicon electrode
104
.
As shown in
FIG. 1B
, a thermal oxidation is carried out to form a gate oxide layer
110
over the substrate
100
in the peripheral circuit region
100
b
. A chemical vapor deposition is next carried out to form a polysilicon layer (not shown in the figure) over the entire silicon substrate
100
. The polysilicon layer is patterned to form a top polysilicon electrode
108
a
above the bottom polysilicon electrode
104
and a polysilicon gate electrode
108
b
in the peripheral circuit region
100
b.
As shown in
FIG. 1C
, conventional processing steps needed to complete the manufacture of source/drain terminals
114
and spacers
112
on the sidewalls of the gate electrode in the peripheral circuit region
100
b
are carried out.
In general, the polysilicon electrodes of a capacitor are doped (for example, using arsenic or phosphorus ions) to increase electrical conductivity. However, when a voltage is applied to the capacitor, electric charges are induced at the junction between the electrode and the inter-electrode dielectric layer. The electric charges near the junction cancel most of the effect of produced by the ionic dopants, thereby creating a depletion region.
The depletion region can be regarded as an extension of the inter-electrode dielectric layer. The presence of the depletion region, therefore, increases the effective dielectric layer of the capacitor. In general, the charge storage capacity of a capacitor is inversely proportional to the thickness of the inter-electrode dielectric layer. In other words, a capacitor having a thin dielectric layer is able to store a greater number of charges. However, the formation of a depletion layer increases the thickness of the dielectric layer, and hence reduces the capacitance of the capacitor. In addition, thickness of the depletion layer varies according to the voltage V applied to the electrodes. This can lead to a variation of the voltage coefficient (1/C(dC/dV)) of a capacitor and hence a de-stabilization of the device. Furthermore, polysilicon has a higher resistivity than other metallic materials. Therefore, polysilicon electrodes often limit the ultimate operating speed and performance of the capacitor.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a capacitor. A semiconductor substrate divided into a peripheral circuit region and a memory cell region is provided. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime, a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of both the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode, and a metallic layer is formed over the dielectric layer to form a capacitor.
In the present invention, the bottom electrode of the capacitor is a metal silicide layer while the top electrode is a metallic layer. Since depletion regions are unable to form in a metal or the metal silicide electrode and the resistivity of metal or metal silicide electrodes is smaller than a conventional polysilicon electrode, operating speed and frequency of the capacitor can be increased.
REFERENCES:
patent: 5393691 (1995-02-01), Hsu et al.
patent: 5866451 (1999-02-01), Yoo et al.
patent: 6054359 (2000-04-01), Tsui
patent: 6075266 (2000-06-01), Yoshitomi
Hou Chia-Hsin
Jung Tz-Guei
Ko Joe
Thomas, Kayden Horstmeyer & Risley
Tsai Jey
United Microelectronics Corp.
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