Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-12
2001-05-15
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S964000
Reexamination Certificate
active
06232178
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for forming a capacitive element in which a plurality of minute capacitive elements having a large electrostatic capacitance are formed by making a surface of a bottom electrode to have hemispherical grains (HSGs), more in detail to the method for forming the minute capacitive elements having the large electrostatic capacitance by injecting dopants at a high concentration into the HSGs of the bottom electrode.
(b) Description of the Related Art
A semiconductor device such as a DRAM includes a capacitive element such as a stacked capacitor and a trench capacitor as a component for a memory cell circuit. The capacitive element generally includes a bottom electrode, a dielectric film and a top electrode.
When a stacked capacitive element is conventionally manufactured, the bottom electrode is formed by growing a polysilicon film on a dielectric film overlying a semiconductor substrate, introducing impurities such as phosphorus into the polysilicon film and patterning the polysilicon film by a photolithographic and etching technique. Then, after a dielectric film such as an oxide film and a nitride film is formed on the bottom electrode, the top electrode is formed, similarly to the bottom electrode, to provide the capacitive element.
With the development of miniaturization and high integration of the semiconductor device, the capacitive element employed as the component thereof is also required to be miniaturized. Recently, a capacitive element for securing a large electrostatic capacitance by employing a small electrode has been realized by increasing a surface area of a bottom electrode having HSGs.
A configuration of the capacitive element having the bottom electrode composed of HSGs will be described referring to
FIGS. 1A and 1B
. The structure of
FIG. 1B
is different from that of
FIG. 1A
only in that the bottom electrode
11
A in
FIG. 1B
has no HSGs while the bottom electrode
11
in
FIG. 1A
has HSGs.
The bottom electrode
11
of the capacitive element is formed on a plug
14
penetrating through an interlayer dielectric film
13
to a silicon substrate
12
as shown in FIG.
1
A. The bottom end of the plug
14
is in contact with a region such as a source diffused region
17
S formed on the silicon substrate
12
. In
FIGS. 1A and 1B
, numerals
17
D and
17
G denote a drain diffused layer and a bit line, respectively.
In
FIG. 1A
, the bottom electrode
11
has on its surface a plenty of HSGs. The respective grains have a mushroom or semispherical convex shape of which a diameter is about between 30 and 70 nm, thereby increasing the surface area of the bottom electrode
11
. The surface area of the bottom electrode
11
having the HSG amounts to about twice that of the bottom electrode
11
A having no HSGs shown in FIG.
1
B.
The bottom electrode having the HSGs is generally is manufactured in accordance with the following process.
A doped amorphous silicon film, for example, a phosphorous (P)-doped amorphous silicon film is formed on a dielectric layer, followed by patterning thereof to form a bottom electrode. Then, the P-doped amorphous silicon film is treated to have the HSGs in accordance with a known process and under known conditions. Then, the bottom electrode having the HSGs is thermally treated at a temperature of 800° C. or more to crystallize the amorphous silicon and to diffuse the phosphorus in the amorphous silicon film into the HSGs to provide the bottom electrode with higher conductivity.
Meanwhile, the thermal treatment temperature of the above capacitive element forming process should be lowered by reasons on structural and circuit designs of the semiconductor device together with the advance of miniaturization and complexity thereof. This is because the components such as transistors mounted together with the capacitive elements on a wafer should be protected from the damage due to exposure to a high temperature during the above thermal treatment
For example, in a 1 G-bit DRAM or a DRAM mounted with a logic circuit, when the thermal treatment of the process of forming the capacitive element is conducted at a temperature of 800° C. or more, impurities in source/drain diffused regions diffuse to shorten a gate length, and impurities (for example, boron) in a gate diffuse to change a threshold voltage of the transistor. in addition, if the wafer having a Ti-silicide film or a Co-silicide film on the surface of the source/drain diffused region or the gate electrode is thermally treated, the silicide film is coagulated to increase the electric resistance. As described above, the thermal treatment at the temperature of 800° C. or more lowers the characteristic of the element such as the transistor, and is hardly conducted reluctantly.
However, the lowering of the thermal treatment temperature below 800° C. reduces a diffusion rate of the phosphorus in the P-doped amorphous silicon film to make difficult the diffusion of the phosphorous through a narrow throat, generally formed at the base of the respective HSGs, into the HSGs. Thus, capacitance reduction due to depletion of the dopant in the HSGs may occur due to the lowering of the diffusion rate.
Then, the capacitance reduction due to the depletion of the dopants in the HSGs will be described referring to
FIGS. 2A and 2B
.
FIG. 2A
is a graph exemplifying an ideal C-V characteristic of a capacitive element, and
FIG. 2B
is a graph exemplifying a curent-voltage characteristic obtained by a thermal treatment for 10 minutes at 800° C. lower than a conventional thermal treatment temperature. In the both graphs, the characteristic of the bottom electrode having the HSGs are compared with that having no HSGs.
The comparison of the graphs of
FIGS. 2A and 2B
indicates that when the thermal treatment temperature after the formation of the HSGs is low, the resultant capacitance significantly reduces due to depleion of the carriers in the HSGs if an applied voltage (V) of a top electrode is lower than the potential of the bottom electrode. In other words, when the applied voltage of the top electrode becomes higher than the potential of the bottom electrode, the capacitance of the N-type bottom electrode slightly increases because electrons are attracted in the bottom electrode, whereas when the applied voltage becomes lower, the electrons in the bottom electrode are expelled to further proceed the depletion of electrons to lower the capacitance.
The phenomenon concerning the dopant depletion of the HSGs will be further described referring to
FIGS. 3A
to
3
C in which a dense hatching part indicates a higher concentration region of impurities (phosphorous) whereas a non-hatching part indicates a lower concentration region.
The interior of the HSGs is non-doped immediately after the treatment for forming the HSGs as shown in
FIG. 3A
, and all the region is a depleted region “E” having substantially no dopant. The succeeding high temperature treatment at 800° C. or more makes the phosphorous sufficiently diffuse from the P-doped amorphous silicon film into the HSGs to extinguish the depleted region “E”.
However, if the thermal treatment is below 800° C., the diffusion rate of the phosphorus in the silicon film is reduced to make it difficult for the dopants to diffuse through the narrow throat at the bases of the HSGs
15
into the bodies of the HSGs
15
. The insufficient diffusion of the phosphorus into the HSGs
15
keeps a most part of the HSGs
15
as a depleted region.
The existence of the depleted region “E” reduces the capacitance due to the above-described reasons when the applied voltage of the top electrode becomes lower.
A phosphorus solid phase diffusion method by employing POCl
3
for suppressing the depletion is described in, for example, JP-A-5(1993)-343614, JP-A-7(1995)-38062 and JP-A-9(1997)-289292.
The method includes to a thermal treatment of a wafer having HSGs at a temperature below 800° C. in a furnace in which the POCl
3
flows. In accordance with the doping of the phosphorus by the
Hutchins, Wheeler & Dittmar
NEC Corporation
Tsai Jey
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