Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1999-05-14
2001-08-21
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S479000, C438S221000
Reexamination Certificate
active
06277703
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for manufacturing an SOI wafer.
BACKGROUND OF THE INVENTION
As known, according to a solution that is currently very widespread in the microelectronics industry, substrates of integrated devices are often formed from wafers of monocrystalline silicon. In the last few years, as an alternative to wafers consisting of silicon alone, composite wafers, so-called “SOI” (Silicon-on-Insulator) wafers have been proposed, having two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer (see for example the article “Silicon-on-Insulator Wafer Bonding Wafer Thinning Technological Evaluations” by J. Hausman, G. A. Spierings, U. K. P. Bierman and J. A. Pals, Japanese Journal of Applied Physics, Vol. 28, No. 8, August 1989, pp. 1426-1443).
Attention has recently been paid to SOI wafers, since integrated circuits that have a substrate formed from wafers of this type have advantages compared with similar circuits formed on conventional substrates, i.e. consisting of monocrystalline silicon alone. These advantages can be summarized as follows:
a) faster switching speed;
b) greater noise immunity;
c) smaller loss currents;
d) elimination of parasitic component switching phenomena (“SCR latch-up”);
e) reduction of parasitic capacitances;
f) greater resistance to radiation effects; and
g) greater packing density of the components.
A typical process for manufacturing SOI wafers is described in the aforementioned article, and is based on physically uniting two monocrystalline silicon wafers (“wafer bonding” process). In particular, according to this process, one of the two wafers is oxidized, and after cleaning operations, is bonded to the other wafer. After thermal annealing, the outer surface of the oxidized wafer is ground and then polished until the required thickness is obtained (for example 1&mgr;m). An epitaxial layer for integrating electronic components is subsequently optionally grown on the thinner monocrystalline silicon layer. The wafers obtained through the conventional wafer bonding method have excellent electrical characteristics, but have undeniably high costs (approximately six times greater than the cost of the standard substrates).
Other methodologies, such as ZHR, SIMOX, etc., are described in the article “SOI Technologies: Their Past, Present and Future” by J. Haisha, Journal de Physique, Colloque C4, Supplément à no. 9, Tome 49, September 1988. These latter techniques have also not yet reached an industrial acceptance, and have some limitations. In fact, they do not provide layers of monocrystalline silicon on large oxide areas. They often have high levels of defects owing to the dislocations generated by stresses induced by the buried oxide, or they do not support formation of high voltage components as with SIMOX technology, where the oxide thickness obtained by oxygen implantation is approximately 100-200 nm.
SUMMARY OF THE INVENTION
The present invention, in one aspect, provides a method for manufacturing SOI wafers, which exploits the intrinsic advantages of microfabrication technologies, but at competitive costs. This method can employ presently available, standard, fully monocrystalline substrates.
In one aspect, the present invention includes a method for manufacturing an SOI wafer comprising: forming, inside a wafer of monocrystalline semiconductor material having a surface, a buried air gap and trenches extending between the buried air gap and the surface; and forming an oxide region inside the buried air gap and the trenches.
In another aspect, the present invention includes a silicon-on-insulator wafer. The wafer includes a substrate of monocrystalline semiconductor material, a plurality of monocrystalline epitaxial regions and an oxide region. The oxide region includes a lower portion interposed between the substrate and the monocrystalline epitaxial regions, and vertical portions extending between the lower portion and an upper surface of the SOI wafer, isolating the monocrystalline epitaxial regions from each other.
In one aspect of the invention, the oxide region is formed by forming a series of implanted regions on a surface of the substrate. The implanted regions have a conductivity different than that of the substrate. An epitaxial layer is grown on the surface of the substrate and on the implanted regions. Trenches are etched through the epitaxial layer to expose portions of the implanted regions, and the implanted regions are selectively removed to convert portions of the epitaxial layer to islands each having a lower surface separated from the surface of the substrate by a gap. Exposed surfaces of the islands and the substrate are oxidized to fill the gaps with silicon dioxide.
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Zorinsky, E.J. et al., “The ‘Islands’ Method—A Manufacturable Porous Silicon SOI Technology.”IEEE, 2:431-434, 1986.
French, P.J. et al., “Epi-micromachining,”Microelectronics Journal, 28:449-464, 1997.
Barlocchi Gabriele
Villa Flavio Francesco
Chaudhuri Olik
Galanthay Theodore E.
Iannucci Robert
Peralta Ginette
Seed IP Law Group PLLC
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