Method for manufacturing an SOI wafer

Details Method for manufacturing an SOI wafer Method for manufacturing an SOI wafer

2002-02-05

2003-05-06

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

On insulating substrate or layer

Reexamination Certificate

active

06559035

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing an SOI wafer.
2. Description of the Related Art
According to current processes known in the microelectronics industry, the substrate of integrated devices is obtained from wafers of monocrystalline silicon. In the last few years, as an alternative to wafers consisting of silicon alone, composite wafers, so-called “SOI” (Silicon-on-Insulator) wafers have been proposed, comprising two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer (see for example the article “Silicon-on-Insulator Wafer Bonding—Wafer Thinning Technological Evaluations” by J. Hausman, G. A. Spierings, U. K. P. Bierman and J. A. Pals, Japanese Journal of Applied Physics, Vol. 28, No. 8, August 1989, pp. 1426-1443).
Considerable attention has recently been paid to SOI wafers, since integrated circuits having a substrate formed from wafers of this type have considerable advantages compared with similar circuits formed on conventional substrates, formed by monocrystalline silicon alone. These advantages can be summarized as follows:
a) faster switching speed;
b) greater immunity to noise;
c) smaller loss currents;
d) elimination of parasitic component activation phenomena (latch-up);
e) reduction of parasitic capacitance;
f) greater resistance to radiation effects; and
g) greater component packing density.
A typical process for manufacturing SOI wafers is described in the aforementioned article, and is based on bonding two monocrystalline silicon wafers (wafer bonding process). In particular, according to this process, one wafer is oxidized, and after cleaning operations, it is bonded to the other wafer. After a thermal annealing step, the outer surface of the oxidized wafer is submitted to surface grinding, polishing until the required thickness is obtained (for example 1 &mgr;m), and buffing. An epitaxial layer, integrating electronic components, is subsequently optionally grown on the thinner monocrystalline silicon layer.
The wafers obtained by the conventional wafer bonding method have excellent electrical features, but have undeniably high costs (approximately six times greater than the cost of the standard substrates).
Other methodologies, such as ZHR, SIMOX, etc., are described in the article “SOI Technologies: Their Past, Present and Future” by J. Haisha, Journal de Physique, Colloque C4, Supplément á no. 9, Tome 49, September 1988. These latter techniques have also not yet reached an acceptable industrial level, and have some limitations. In fact, they do not allow obtainment of monocrystalline silicon layers on extensive oxide areas, they have a high defect level owing to displacements generated by stresses induced by the covered oxide, or they do not allow application of high voltages as with SIMOX technology, wherein the oxide thickness obtained by oxygen implant is approximately 100-200 nm.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a process for manufacturing an SOI wafer which exploits at least some of the inherent advantages of these technologies, but at competitive costs with respect to standard, fully monocrystalline substrates now being used.
On a wafer of monocrystalline semiconductor material, first protective regions of an oxidation resistant material are formed, covering first wafer portions. Deep trenches are formed in said wafer, extending between and laterally delimiting said first wafer portions. Said first wafer portions are oxidized, except upper portions, forming at least one continuous region of covered oxide overlaid by said non-oxidised upper portions, and covered by said first protective regions. Said first protective regions are removed, and a crystalline semiconductor material layer is epitaxially grown from said upper portions.


REFERENCES:
patent: 4361600 (1982-11-01), Brown
patent: 4563227 (1986-01-01), Sakai et al.
patent: 4704186 (1987-11-01), Jastrzebski
patent: 4760036 (1988-07-01), Schubert
patent: 4845048 (1989-07-01), Tamaki et al.
patent: 4910165 (1990-03-01), Lee et al.
patent: 4948456 (1990-08-01), Schubert
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5208167 (1993-05-01), Nakamura
patent: 5336633 (1994-08-01), Tsuruta
patent: 5382534 (1995-01-01), Sheu et al.
patent: 5635411 (1997-06-01), Takasu
patent: 5712205 (1998-01-01), Park et al.
patent: 5877092 (1999-03-01), Lee et al.
patent: 6013937 (2000-01-01), Beintner et al.
patent: 6350657 (2002-02-01), Mastromatteo et al.
patent: 6362070 (2002-03-01), Villa et al.
patent: 6455391 (2002-09-01), Villa et al.
patent: 0 223 694 (1987-05-01), None
patent: 0 226 091 (1987-06-01), None
patent: 0 488 344 (1992-06-01), None
patent: 2 489 041 (1982-02-01), None
patent: 2 156 149 (1985-10-01), None
patent: 0 130 724 1 (1989-12-01), None
patent: 0 534 332 0 (1993-12-01), None
Zorinsky et al., “The ‘Islands’ Method—A Manufacturable Porous Silicon SOI Technology,”IEEE, 2:431-434, 1986.
Haisma, J., “SOI Technologies: Their Past, Present and Future,”Journal de Physique49(9):C4-3-C4-12, Sep. 1988.
Haisma, J., et al., “Silicon-on-Insulator Bonding-Wafer Thinning Technological Evaluations,”Japanese Journal of Applied Physics28(8):1426-1443, Aug. 1989.
Kakoschke, R. et al., “Trench Sidewall Implantation with a Parallel Scanned ION Beam,”IEEE Trans. Elec. Dev, pp. 1-9, Nov. 1989.
Murari, B., Bertotti, F. Vignola, G.A. (Eds.),Smart Power Ics, pp. 20-21, Springer, New York, 1995.
Yasseen, A. et al., “Chemical-Mechanical Polishing for Polysilicon Surface Micromachining,”J. Electrochem. Soc. 144(1):237-242, Jan. 1997.
French et al., “Epi-Micromachining,”Microelectronics Journal, 28:449-464, 1997.

Affiliated with

Also associated with

Rating

Method for manufacturing an SOI wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing an SOI wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing an SOI wafer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3059304