Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-28
2001-08-14
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S271000, C438S242000, C438S589000
Reexamination Certificate
active
06274431
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is directed to integrated circuit arrangements having at least one MOS transistor and to methods for the manufacture thereof.
In integrated circuit arrangements, MOS transistors and logic gates are currently usually realized in a planar silicon technology, whereby source, channel region and drain are laterally arranged. The channel lengths that can be achieved are thereby dependent on the resolution of the optical lithography employed and on tolerances in the structuring and alignment. Typical channel lengths of 0.6 &mgr;m are achieved in the 16 M generation, 0.35 &mgr;m in the 64 M generation.
A further shortening of the channel lengths of MOS transistors is desirable, for example in circuit arrangements in which fast switching events are required, which is usually the case in logic processing. The packing density of a circuit arrangement can also be increased by MOS transistors with short channel lengths. The space-consuming, large channel width that is otherwise necessary can be foregone by employing short channel lengths, specifically when processing high current intensities in, for example, line drivers.
Some possibilities for reducing the channel length have been disclosed. However, the step from the fabrication of a single unit to mass production is time-consuming and costly, specifically in semiconductor technology. New, improved circuit structures are therefore especially attractive for semiconductor manufacture when it is only the existing know-how that has to be recoursed, insofar as possible. This economic aspect is not satisfied by the prior proposals for realizing shortened channel lengths.
For example, it was proposed that shorter channel lengths be achieved in planar MOS transistors by replacing the optical lithography with electron beam lithography, a resolution of which is significantly better (see, for example, T. Mizuno, R. Ohba, IEDM Tech. Dig., p.109 (1996)). Individual, functional MOS transistors with channel lengths as short as 50 nm have hitherto been successfully produced with an electron beam printer on a laboratory scale. Although known layouts that must merely be miniaturized can be employed with this technology, electron beam lithography is slow; as a result thereof, it seems unsuitable for employment in semiconductor manufacture.
Masks are under-etched, i.e. hollowed out underneath, by isotropic over-etching of layers, as a result of which smaller structural sizes than those belonging to lithography can likewise be produced. However, it is difficult to achieve reproducible results with this technique, for which reason it will presumably also not be employed on a broad basis in semiconductor manufacture.
Further possibilities of obtaining short channel lengths are available given a channel path that is perpendicular to the surface of the circuit arrangement instead of parallel. Transistors having a perpendicular channel course are referred to as “vertical transistors”. The channel length is thereby determined by the layer thickness of the channel region and is thus independent of the resolution of the lithography employed.
A circuit arrangement of integrated MOS transistors has been disclosed whose source, channel region and drain are stacked above one another as layers (see German Letters Patent DE 4340967 C1). The contacting of source, drain and gate electrode of such an MOS transistor, accordingly, occurs differently than given planar transistors. At least two of the layers are grown by epitaxy. A depression that has its sidewalls provided with a gate dielectric and a gate electrode is etched into this layer sequence. A channel length as short as less than 50 nm is achieved by this procedure. What is especially disadvantageous is the increased process expense when incorporating this circuit arrangement into semiconductor manufacture due to the manufacturing method that clearly differs from the traditional manufacturing method.
SUMMARY OF THE INVENTION
It is an object of the invention to specify an MOS transistor that is situated within an integrated circuit arrangement, and which has an especially short channel length and can be integrated into the semiconductor manufacture with reduced expense. Furthermore, a manufacturing method is provided for such an MOS transistor incorporated in an integrated circuit arrangement.
This problem is solved by a vertical MOS transistor that is surrounded by a traditional insulation structure. A transistor at one sidewallis designed of a depression. The transistor is individually driveable and can be manufactured by use of a layout of traditional planar transistors, except for one or a few additional masks. Source/drain regions are arranged diagonally offset relative to one another, i.e. laterally and at different depths. The flow of current proceeds essentially perpendicular to the surface of the circuit arrangement.
The layout of the traditional planar transistors is employed for manufacturing a circuit arrangement of the invention, with the difference that a gate mask employed for the generation of a gate electrode is shortened compared to a gate mask for generating the traditional planar transistors in the region of the MOS transistor. One of the additional masks is employed for generating the depression.
The term “channel width” describes the dimension of the channel perpendicular to the flow of current and parallel to the gate electrode.
The term “junction depth” describes the path along which the source/drain regions have minimal spacing from one another, namely perpendicular to the flow of current and perpendicular to the gate electrode.
Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. The invention makes it possible to process circuit arrangements that were fabricated in planar technology with the assistance of the few additional masks with transistors having a considerably shorter channel length, but the same channel width. Merely due to the contacting of source and drain that clearly differs from planar transistors, new masks and a layout differing completely from the layout of traditional planar transistor are required for the manufacture of previously described vertical MOS transistors. The employment of already existing masks for MOS transistors of the invention considerably reduces the expense required, given integration into semiconductor manufacture.
A further advantage of employing masks that are already present is the easier incorporation of the new circuit structure into circuit arrangements that also comprise known elements.
The designs of known circuit arrangements can be largely accepted, since only a slight modification has to be undertaken at the locations at which improved transistors are needed.
Except for height variations of approximately 150 nm, the surface of the circuit arrangement looks like that of traditional circuit arrangements, this making this invention especially attractive for the layout designer.
The sequence of process steps is essentially the same as in the production of the traditional planar transistors.
The same materials as in the production of the traditional planar transistors can be employed.
Complicated method steps, such as electron beam lithography, and techniques susceptible to malfunction, such as over-etching, are not necessary given the employment of vertical transistors.
A further advantage of the invention is that the simultaneous manufacture of the source/drain regions by implantation —which, by contrast to other vertical transistors, is possible due to the lateral arrangement of these regions —represents a step in the traditional manufacturing process.
The lateral arrangement also offers the advantage that the channel region can be easily connected to a fixed potential, as a result whereof leakage currents and changes in the cutoff voltage are kept small.
Together with the vertical arrangement of source and drain, the lateral arrangement yields a junction depth that is small even compared to planar transistors.
Negative effe
Aeugle Thomas
Krautschneider Wolfgang
Risch Lothar
Roesner Wolfgang
Chaudhuri Olik
Rao Shriniva H.
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
LandOfFree
Method for manufacturing an integrated circuit arrangement... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing an integrated circuit arrangement..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing an integrated circuit arrangement... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2541056