Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-30
2002-10-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C438S275000, C438S279000, C438S981000
Reexamination Certificate
active
06465307
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor devices and, more specifically, to a method for manufacturing an asymmetric input/output (“I/O”) transistor.
BACKGROUND OF THE INVENTION
Semiconductor devices are used for many applications. One component used extensively in semiconductor devices is a transistor. There are many different types of transistors, including core transistors and input/output (“I/O”) transistors. Typically, core transistors exist in a center region of a semiconductor chip while I/O transistors are dispersed around the perimeter of the chip. Additionally, core transistors usually run at a lower voltage than I/O transistors. The performance of I/O transistors is important for chip manufacturers to be competitive in the networking chip business (such as chips for routers).
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method of forming an asymmetric input/output (“I/O”) transistor includes providing a semiconductor substrate having a core transistor region and an I/O transistor region, forming a first oxide layer outwardly from the semiconductor substrate, masking a first portion, less than a whole portion, of the I/O transistor region with a first photoresist layer, removing the first oxide layer from the core transistor region and a second portion of the I/O transistor region, removing the first photoresist layer, forming a second oxide layer outwardly from the substrate in the core transistor region and the second portion of the I/O transistor region and outwardly from the first oxide layer in the first portion of the I/O transistor region, forming a polysilicon layer outwardly from the second oxide layer, removing a portion of the polysilicon layer, the second oxide layer, and the third oxide layer to form gates for the core transistor region and the I/O transistor region, masking the first portion of the I/O transistor region with a second photoresist layer, doping a source region and a drain region of the core transistor region and a source region of the I/O transistor region with a first dopant, doping the source region and the drain region of the core transistor region and the source region of the I/O transistor region with a second dopant, removing the second photoresist layer, masking the core transistor region and the second portion of the I/O transistor region with a third photoresist layer, and doping a drain region of the I/O transistor region with a third dopant.
Embodiments of the invention provide a number of technical advantages. Embodiments of the invention may include all, some, or none of these advantages. For example, having an asymmetric input/output transistor may produce more drive current as well as improve the channel-hot carriers (“CHC”) lifetime because of the graded drain profile. In some embodiments, a chip designer may be able to tailor the off current, I
off
.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5580804 (1996-12-01), Joh
patent: 5789787 (1998-08-01), Kadosh et al.
patent: 5801416 (1998-09-01), Choi et al.
patent: 5989962 (1999-11-01), Holloway et al.
patent: 6025234 (2000-02-01), Chou
patent: 6063670 (2000-05-01), Lin et al.
patent: 6087223 (2000-07-01), Ra
patent: 6110783 (2000-08-01), Burr
patent: 6194270 (2001-02-01), Bottini et al.
patent: 6200863 (2001-03-01), Xiang et al.
patent: 6221716 (2001-04-01), Lee et al.
patent: 6261978 (2001-07-01), Chen et al.
“Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub-50nm Gate Length CMOS Devices,” T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi, M. Bohr, Portland Technology Development, TCAD, Intel Corporation, Hillsboro (2001 Symposium on VLSI Technology Digest of Technical Papers, p. 17).
“Asymmetrically-Doped Buried Layer (ADB) Structure for Low-Voltage Mixed Analog-Digital Applications,” Masafumi Miyamoto, Kenji Toyota, Koichi Seki, and Takahiro Nagano, Semiconductor Development Center, Central Research Laboratory, Hitachi, Ltd. 1-280, Higashi-koigakubo, Kokubuni, Tokyo 185, Japan (1996 Symposium on VLSI Technology Digest of Technical Papers, p. 102).
“Graded Gate VDMOSFET,” Shuming Xu, Kian Paau Gan, Pang Dow Foo, Yi Su, and Yong Liu (IEEE Electron Device Letters, vol. 21, No. 4, Apr. 2000).
“Lateral Thinking About Power Devices (LDMOS),” Taylor R. Efland, Chin-Yu Tsai, Sameer Pendharkar (Power Device Development, Mixed Signal Productization, Texas Instruments Incorporated, Dallas, Texas, USA).
“RF LDMOSFET with Graded Gate Structure,” Xu, Shuming, and Foo, Pan Dow (Institute of Microelectronics, 10 Science Park Road, #02-19/26 (The Alpha, Singapore Science Park II, Singapore 117684, p. 221).
“Transistor Design Issues in Integrating Analog Functions with High Performance Digital CMOS,” A. Chatterjee, K. Vasanth, D. T> Grider, M. Nandakumar, G. Pollack, R. Aggarwal, M. Rodder and H. Schichijo (Silicon Technology Development, Texas Instruments, Dallas, USA, p. 11A-1).
Chidambaram P R
Rodriguez John A.
Brady III W. James
Garner Jacqueline J.
Kennedy Jennifer M.
Niebling John F.
Telecky , Jr. Frederick J.
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