Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-03-15
2011-03-15
Pham, Hoai V (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C257SE21632
Reexamination Certificate
active
07906387
ABSTRACT:
A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.
REFERENCES:
patent: 4801555 (1989-01-01), Holly et al.
patent: 7615430 (2009-11-01), Pawlak
patent: 2004/0171202 (2004-09-01), Kim
patent: 10-2006-0006593 (2006-01-01), None
Jeong Hyeon Park; “Method for Fabricating High Voltage Transistor to Reduce Design Rule”; Korean Patent Abstracts; Publication No. 1020060006593 A; Publication Date: Jan. 19, 2006; Korean Intellectual Property Office, Republic of Korea.
Korean Office Action dated Jun. 1, 2009; Korean Patent Application No. 10-2007-0138833; Korean Intellectual Property Office, Republic of Korea.
Chinese Office Action with English Translation date stamped Jan. 15, 2010; Chinese Patent Application No. CN2008101888274; 10 pgs.; The State Intellectual Property Office of P.R.C., People's Republic of China.
German Office Action dated Aug. 6, 2010; German Patent Application No. P2008, 1070 DE N; 3 pages; German Patent and Trademark Office, Germany.
Dongbu Hi-Tek Co., Ltd.
Fortney Andrew D.
Pham Hoai v
The Law Offices of Andrew D. Fortney
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