Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-15
2004-01-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S718000, C438S191000, C438S197000
Reexamination Certificate
active
06673667
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a monocrystalline material layer comprised of semiconductor material, compound semiconductor material, and/or other types of material such as metals and non-metals.
In particular, the present invention provides a method for manufacturing a semiconductor that aids in carrying out photolithography operations during manufacturing semiconductor devices involving multiple semiconductor materials within a single integral monolithic apparatus. The present invention provides improved alacrity and efficiency in manufacturing such multi-material integral monolithic semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor devices often include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and band gap of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases.
For many years, attempts have been made to grow various monolithic thin films on a foreign substrate such as silicon (Si). To achieve optimal characteristics of the various monolithic layers, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow various monocrystalline layers on a substrate such as germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting layer of monocrystalline material to be of low crystalline quality.
If a large area thin film of high quality monocrystalline material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in or using that film at a low cost compared to the cost of fabricating such devices beginning with a bulk wafer of semiconductor material or in an epitaxial film of such material on a bulk wafer of semiconductor material. In addition, if a thin film of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material.
Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline film or layer over another monocrystalline material and for a process for making such a structure. In other words, there is a need for providing the formation of a monocrystalline substrate that is compliant with a high quality monocrystalline material layer so that true two-dimensional growth can be achieved for the formation of quality semiconductor structures, devices and integrated circuits having grown monocrystalline film having the same crystal orientation as an underlying substrate. This monocrystalline material layer may be comprised of a semiconductor material, a compound semiconductor material, and other types of material such as metals and non-metals.
A significant problem encountered during semiconductor manufacturing of integral monolithic devices involves limitations in employing lithographic manufacturing equipment in such operations. Lithographic manufacturing equipment is a common manufacturing tool for producing densely populated integrated circuitry that is desirable in today's market in which smaller, more compact products are constantly sought. Photolithographic equipment is optically-based equipment that has a depth of focus (depth of field) within which it must operate. Operation of photolithographic equipment outside its prescribed depth of focus is not practical, feasible or desirable.
As a consequence of the focal limitations of lithographic equipment, it is desirable that there be a coplanar relation among various lands, or areas, in which lithographic processes are to be practiced. Thus, using the processing technology taught by the present application one may, for example, require that top surfaces of gallium arsenide (GaAs) lands and top surfaces of silicon (Si) lands in an integral monolithic structure must be substantially coplanar. Such coplanarity assures that lithographic processes only need to deal with a single depth of focus for manufacturing the part involved. For example, it would be useful to be able to use coplanar alignment keys in manufacturing MOSFET devices (in silicon) and MESFET devices (in gallium arsenide) in a single semiconductor device using common alignment keys. Such common alignment keys would allow one to perform operations in either silicon or in gallium arsenide at any time during manufacturing operations without needing to reset lithographic equipment.
If the various lands are not coplanar to an extent that they are misaligned by a distance greater than the depth of focus of the lithographic equipment employed, then a product designer must decide where to establish alignment markings, or keys for registration of lithographic equipment for each set of coplanar lands implemented in a respective material. In such situations, there may likely be a need for more than one set of alignment keys. Such an arrangement is not desirable because the lithographic equipment must be reset to a different orientation for processing each material. That is, the lithographic equipment would have to be adjusted or reset to ensure that a particular land implemented in a respective material is within the depth of focus for the lithographic equipment. Such occasions for resetting equipment are disruptive to a manufacturing operation, provide unwanted opportunities for introduction of errors into the manufacturing process and generally contribute to inefficiency. Inefficiency is readily manifested as increased cost in manufacturing because of greater amounts of waste, lower yields and similar related factors.
The capability for multi-material semiconductor devices in an integral monolithic structure provided by the present invention has not been available to product designers or manufacturing process designers heretofore. Until now different semiconductor technologies were implemented separately on discrete chips or substrates and then mechanically combined in a single product. That is, no capability to produce multi-material integrated monolithic semiconductor devices has been available before. Now one can employ the present invention to efficiently and reliably produce multi-material integrated monolithic semiconductor devices.
The need for coplanarity among materials in different lands in an integral monolithic semiconductor apparatus is met using the method of the present invention. The present invention provides a method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantia
Cornett Kenneth D.
Gorrell Jonathan F.
Lindsay Jr. Walter L.
Motorola Inc.
Niebling John F.
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