Method for manufacturing a semiconductor memory device with...

Details Method for manufacturing a semiconductor memory device with... Method for manufacturing a semiconductor memory device with...

2000-08-03

2002-04-23

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S301000

Reexamination Certificate

active

06376295

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device capable of electrically rewriting, particularly to a technique for forming a memory cell with a fine structure.
2. Related Background Art
FIG. 1
is a view showing a sectional structure of a cell of a conventional M(O)NOS type EEPROM. A memory cell of
FIG. 1
has a memory cell transistor
53
formed on the upper surface of a p-type well area
52
on an n-type silicon substrate
51
, and first and second selecting transistors
54
and
55
. A gate insulating film
56
of the memory cell transistor
53
has a laminated structure constituted of a silicon oxide film
57
, a silicon nitride film
58
, a tunnel oxide film
59
, and the silicon nitride film
58
is utilized as an electric charge accumulating layer of electrons injected through a direct tunnel from the substrate
52
.
When data is written to the EEPROM having the structure as shown in
FIG. 1
, data are first erased from all the memory cells in a predetermined cell block. Specifically, a positive high voltage is applied to the p-type well area
52
, and electrons are discharged to the p-type well area
52
from the silicon nitride film
58
through the direct tunnel, whereby all the memory cells are in normally on states.
Next, data is written to a desired memory cell. Specifically, by designating the first selecting transistor
54
, a control gate of the memory cell transistor
53
, and a bit line (not shown), an arbitrary memory cell is selected. The writing to the memory cell transistor
53
is performed by setting the bit line to a ground level, and applying a high voltage to the first selecting transistor
54
and the control gate
53
, while the second selecting transistor
55
is turned off, whereby electrons are injected to the silicon nitride film
58
from the substrate
52
through the direct tunnel.
The control gate
53
of
FIG. 1
is shared by a plurality of memory cells, and in order to avoid the writing of the data to a non-selected memory cell, the bit line of the non-selected memory cell is set to an intermediate voltage. Moreover, the second selecting transistor
55
is set to an off state so that no through current may flow from the bit line to a source side.
The EEPROM of
FIG. 1
has the following problems (1) and (2):
(1) Since each memory cell requires two selecting transistors
54
and
55
, a cell size is unavoidably enlarged, and it is difficult to enlarge a memory capacity.
(2) Since there is provided a structure in which the electric charge written to the silicon nitride film
58
passes toward the substrate by direct tunneling and a so-called electric charge falling easily occurs, a charge holding property is inferior.
As one technique for solving the above problems (1) and (2), a virtual ground array type EPROM or EEPROM is proposed.
FIG. 2
is a schematic sectional view of the virtual ground array type EEPROM, and
FIG. 3
is a circuit diagram showing an inner configuration of the virtual ground array type EPROM.
In the virtual ground array type EEPROM or EPROM, as shown in
FIG. 3
, there is provided a memory cell array
2
in which a plurality of memory cells are arranged in a matrix manner. Control gates in the memory cells of the same row in the memory cell array
2
are connected in common to constitute a word line. Moreover, sources and drains of memory cells
1
adjacent to each other in a column direction are interconnected, and sources and drains of the same column are connected in common to constitute a column line.
As shown in
FIG. 2
, each memory cell
1
is provided with a floating gate
61
and a control gate
62
, and in a lower semiconductor substrate
63
, n
+
diffusion layer
64
and n
−
diffusion layer
65
are formed for use as a source area and a drain area. Specifically, the n
+
diffusion layer
64
forms the source area, and the n
−
diffusion layer
65
forms the drain area. Moreover, the floating gate
61
is formed to overlap the n
+
diffusion layer
64
and the n
−
diffusion layer
65
.
When data is written to the EEPROM of
FIG. 2
, the source diffusion layer is set to a ground level, and a high voltage is applied to the word line and the drain diffusion layer. Thereby, hot electrons are injected to the floating gate
61
from the drain side.
For the non-selected cell adjacent to the source side of the selected cell, data writing is avoided by setting the drain diffusion layer to the ground level. Moreover, for the non-selected cell adjacent to the drain side of the selected cell, the data writing is avoided by setting the drain diffusion layer and the source diffusion layer to the same potential, whereby, program current is reduced.
The EEPROM of
FIG. 2
has the following problems (3) and (4):
(3) During writing, a large amount of the program current having a mA level flows in a single unit of memory cell
1
.
(4) For patterns to form diffusion layer wiring, selecting transistors, and the like, since voltage drop is relatively large, writing properties are deteriorated, and a dispersion of threshold voltage is also enlarged. Therefore, it is difficult to simultaneously write to multiple bias.
(5) Since there is provided a two-layer gate structure, the structure is complicated, and manufacturing processes also become complicated.
As described above, because of the problems (3) to (5), even when EEPROM circuit structure is of the virtual ground array type, good electric properties cannot be obtained. As a result, it becomes difficult to enlarge the memory capacity.
When data is erased from EPROM of
FIG. 3
, ultraviolet rays are radiated from above the semiconductor substrate, and electrons are discharged from the floating gate. Moreover, data is read from EPROM of
FIG. 3
in the following procedure. For example, when data is read from a memory cell
1
a
of
FIG. 3
, all selection gates SG
1
to SG
4
are set to power supply voltage Vdd, a gate line Gn connected to the memory cell
1
a
is set to the power supply voltage Vdd, the other gate lines are set to ground voltage Vss, all source contacts on the left side from source contact SC
1
are set to the ground voltage Vss, all source contacts on the right side from source contact SC
2
are set to the power supply voltage Vdd, all drain contacts on the left side from drain contact DC
1
are set to the ground voltage Vss, and all drain contacts on the right side from drain contact DC
2
are set to the power supply voltage Vdd, so that “0” or “1” is distinguished in accordance with the amount of electric current flowing into the drain contact DC
2
.
Similarly, when data is read from memory cells
1
b
,
1
c
and
1
d
of
FIG. 3
, voltages as shown in
FIG. 4
are applied to the selection gates SG
1
to SG
4
, gate lines G
1
to Gm, source contacts SC
1
to SC
3
, and drain contacts DC
1
to DC
3
, respectively.
On the other hand, data is written to EPROM of
FIG. 3
in the following procedure. For example, when data is written to the memory cell
1
a
of
FIG. 3
, all the selection gates SG
1
to SG
4
are set to power supply voltage Vdd, the gate line Gn connected to the memory cell
1
a
is set to a voltage Vpd which is higher than the power supply voltage Vdd, the other gate lines are set to the ground voltage Vss, all the source contacts on the left side of the source contact SC
1
are set to the ground voltage Vss, all the source contacts on the right side of the source contact SC
2
are set to the voltage Vpd, all the drain contacts on the left side of the drain contact DC
1
are set to the ground voltage Vss, and all the drain contacts on the right side of the drain contact DC
2
are set to the voltage Vpd. In this state, electrons are injected to the floating gate from a channel section of the memory cell
1
a
. By the above-described operation, the threshold voltage of the memory cell
1
in which the electrons are injected to the floating gate can be set to be higher than the power supply voltage Vdd.
Similarly, a method of setting voltages whe

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