Method for manufacturing a semiconductor memory cell and a polys

Details Method for manufacturing a semiconductor memory cell and a polys Method for manufacturing a semiconductor memory cell and a polys

1996-05-30

1997-04-22

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

257904, 438385, 438659, H01L 2170, H01L 2700, H01L 218244

Patent

active

056228848

ABSTRACT:
A method is provided for manufacturing a polysilicon load resistor of a semiconductor memory cell. The semiconductor memory cell is formed with at least one transistor and has a semiconductor substrate with a gate dielectric layer on a portion thereof, and a gate electrode layer over the gate dielectric layer. The method includes the steps of: (a) depositing a insulating layer over the gate electrode layer and the remaining portion of the semiconductor substrate around the gate electrode and gate dielectric layers; (b) depositing a polysilicon layer over the insulating layer; (c) implanting ions in the polysilicon layer so as to adjust resistance thereof; (d) etching the polysilicon layer so as to form a high resistance load resistor; (e) etching the insulating layer so as to expose a portion of the gate electrode layer; and (f) forming a metal contact at two ends of the load resistor, one of the metal contacts being located on the exposed portion of the gate electrode so as to establish electrical connection between the gate electrode layer and the load resistor.

REFERENCES:
patent: 5108945 (1992-04-01), Matthews
patent: 5159430 (1992-10-01), Manning et al.
patent: 5179033 (1993-01-01), Adan
patent: 5232865 (1993-08-01), Manning et al.
patent: 5418393 (1995-05-01), Hayden
patent: 5514617 (1996-05-01), Liu

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