Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-05
2003-03-11
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S241000, C438S526000
Reexamination Certificate
active
06531363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit of triple well structure.
2. Description of Related Art
In the prior art, a reduced power consumption is strongly demanded in a semiconductor integrated circuit such as DRAM and SRAM. One effective approach is to lower a power supply voltage. However, it is in many cases that an external power supply voltage Vext is fixed and therefore can be freely set. In many cases, therefore, the lowering of the power supply voltage is realized by maintaining the external power supply voltage Vext as it is but lowering only an internal power supply voltage Vint used in the inside of the semiconductor integrated circuit chip.
When two different power supply voltages of the external power supply voltage Vext and the internal power supply voltage Vint are used in the semiconductor integrated circuit of a CMOS structure, two kinds of N-wells become necessary. Namely, an N-well set to the external power supply voltage Vext and another N-well set to the internal power supply voltage Vint become necessary. A well structure capable of realizing this demand is exemplified by a well structure in which N-wells
103
and
105
are formed in a surface region of a P-type silicon substrate
101
as shown in FIG.
16
.
However, when this well structure is adopted in the semiconductor integrated circuit such as DRAM and SRAM, a problem is encountered. Now, this problem will be described with reference to a DRAM as an example.
FIG. 17
is an equivalent circuit of a typical DRAM memory cell. In
FIG. 17
, the memory cell is constituted of one capacitor
150
and one NMOS transistor
151
. A gate of the NMOS transistor
151
is connected to a word line
152
, and one of a source and a drain of the NMOS transistor
151
is connected to a bit line
153
. The other of the source and the drain of the NMOS transistor
151
is connected to the memory cell capacitor
150
, Incidentally, a condition that an electric charge is accumulated in the memory cell capacitor
150
, corresponds to a information holding condition.
In order to access the memory cell, a potential of the word line
152
is elevated so as to turn on the NMOS transistor
151
. In this condition, information can be written into and read out from the memory cell capacitor
150
through the bit line
153
. The above is an operation principle of the memory cell.
In the DRAM, a number of memory cells having the above mentioned structure are arranged in the form of a matrix array. These memory cell array is formed in a P-well. Incidentally, not only the memory cell array but also a peripheral circuit and an input/output circuit are formed in the DRAM.
When the DRAM is formed as shown in
FIG. 16
, all P-wells including a P-well
102
in which the memory cell array is formed, are electrically connected to one another through the substrate. As a result, the following problem is encountered.
Namely, a negative potential is applied to an input/output terminal, electrons are emitted to a P-well
104
from an n
+
diffused layer
108
connected to the input/output terminal, and these emitted electrons reach to the P-well
102
of a memory cell zone
113
through the substrate
101
, and further enter to an n
+
diffused layer
110
within this well
102
, thereby to resultantly cancel the electric charges of a memory cell capacitor
111
connected to the n
+
diffused layer
110
.
Furthermore, electrical noises generated in a P-well of a peripheral circuit zone propagate to the P-well
102
of the memory cell zone
113
. As a result, an adverse influence occurs that information of the memory cell cannot be properly read out.
In addition, since the potential of all the P-well must be made in common, it is impossible to set the potential of the P-well
102
of the memory cell zone
113
to a negative level in order to prevent a soft error and to elevate a breakdown voltage of the device isolation, and on the other hand to maintain the P-well of the peripheral circuit at a ground potential in order to prevent a latch-up phenomenon.
In order to prevent the above mentioned problem, for example, Japanese Patent Application Pre-examination Publication No. JP-A-09-055483 and its corresponding U.S. Pat. No. 5,668,755 (the content of which is incorporated by reference in its entirety into this application) propose a triple well structure. Now, this triple well structure will be described with reference to FIG.
18
. As shown in
FIG. 18
, in an N type silicon substrate
121
, a buried P-type layer
124
is formed in addition to N-wells
125
and
126
and P-wells
122
and
123
. The N-well
125
is surrounded by the P-well
123
and the buried P-type layer
124
so that the N-well
125
is electrically isolated from the N type silicon substrate
121
. An internal power supply voltage Vint is applied to the N-well
125
surrounded by the buried P-type layer
124
, and an external power supply voltage Vext is applied to the N-well
126
which is not surrounded by the buried P-type layer
124
. The P-wells
122
and
123
are electrically isolated from each other since the substrate is of the N type.
In this triple well structure, not only the two different wells of the N-well
125
set to the internal power supply voltage Vint and the N-well
126
set to the external power supply voltage Vext can be used, but also the P-wells are electrically isolated from each other. Therefore, even if a negative potential is applied to the input/output terminal so that electrons are emitted from an n
+
diffused layer connected to the input/output terminal, the electrons are absorbed by the N type silicon substrate
121
, and therefore, the electrons do not reach the P-well
122
of a memory cell zone
113
. Accordingly, even if a negative potential is applied to the input/output terminal, there is no fear that the information of the memory cell is erased.
Furthermore, since the P-well
122
of the memory cell zone
113
is electrically isolated from a P-well of a peripheral circuit zone by the N type silicon substrate
121
, the electrical noises generated in the peripheral circuit zone never propagate to the memory cell zone
113
, so that the information of the memory cell is never lost.
In addition, since the P-well
122
of the memory cell zone
113
is electrically isolated from P-wells of the peripheral circuit zone and an input/output circuit zone by the N type silicon substrate
121
, it is possible to set the potential of the P-well of the memory cell zone
113
to a negative level in order to prevent a soft error and to elevate a breakdown voltage of the device isolation, and on the other hand to maintain the P-wells of the peripheral circuit zone and an input/output circuit zone at a ground potential in order to prevent a latch-up phenomenon.
Since the triple well structure has many advantages as mentioned above, this triple well structure is adopted in many DRAMs and many SRAMs.
On the other hand, not only the reduced power consumption but also a high speed operation are demanded in the semiconductor integrated circuit. For the high speed operation, it is required to increase an ON current of MOSFETs. One means for increasing the ON current is to thin a gate oxide film. However, if only the gate oxide film is thinned while maintaining the power supply voltage, an electric field applied to the gate oxide film becomes strong, with the result that reliability of the gate oxide film can no longer be ensured. Therefore, in order to thin the gate oxide film, it is necessary to lower the power supply voltage.
However, as mentioned hereinbefore, even if it is possible to lower the internal power supply voltage Vint used in the inside of the chip, it is impossible in many cases to arbitrarily lower the external power supply voltage Vext supplied from an external circuit, since the external power supply voltage Vext is previously set in accordance with a standard. In this case, the thickness of the gate oxide film mu
Chaudhuri Olik
Estrada Michelle
NEC Corporation
LandOfFree
Method for manufacturing a semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3002582