Method for manufacturing a semiconductor device having a low...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S308000, C438S514000, C438S519000, C438S522000

Reexamination Certificate

active

07129141

ABSTRACT:
A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.

REFERENCES:
patent: 5654209 (1997-08-01), Kato
patent: 6091113 (2000-07-01), Tanaka
patent: 6709906 (2004-03-01), Yamaguchi et al.
patent: 64-32640 (1989-02-01), None
patent: 3212150 (2001-07-01), None
patent: 1996-11638 (1996-08-01), None
patent: 2002-25830 (2002-04-01), None
T. Umeda, et al., “Defects related to DRAM leakage current studied by electrically detected magnetic resonance”, vol. 308-310, pp. 1169-1172, 2001.
Korean Office Action dated Jun. 9, 2006 with a partial English translation.

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