Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-17
2003-07-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S393000, C438S250000, C438S618000
Reexamination Certificate
active
06596581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device having a metal-insulator-metal capacitor and a damascene wiring layer structure.
2. Description of the Related Art
As the integration density of semiconductor devices increases, a metal wiring layer process becomes more important in determining the performance and reliability of semiconductor devices. Recently, aluminum (Al) has been primarily used as a wiring layer material. Aluminum (Al) has a relatively low resistivity of about 3-4 &mgr;&OHgr;-cm and may be easily manipulated. However, as the line width of wiring layers decreases while the length of wiring layers increases, a material having a resistivity lower than that of aluminum is needed.
Copper (Cu) is the most promising substitute for aluminum in highly-integrated circuits because copper has a very low resistivity of about 1.7 &mgr;&OHgr;-cm. In addition, copper has superior electromigration resistance. Accordingly, even if the cross-sectional area of copper wiring layers continues to decrease, the operational speed and reliability of semiconductor devices may be maintained. However, it is difficult to pattern copper wiring layers using photolithography, and thus a dual damascene process is used to form such copper wiring layers.
In a conventional method for manufacturing metal wiring layers, a metal is deposited first and then is patterned by photolithography, thereby forming an interlayer insulating layer. In the damascene process, however, an interlayer insulating layer is formed first, a trench, which corresponds to a metal wiring layer region and a via, is formed, and then the trench is filled with metal. More specifically, in a dual damascene process, a metal wiring layer region trench and a via trench are formed by performing two photolithographic processes and two etching processes and then are chemically and mechanically polished, thereby forming a metal wiring layer region and a via.
In order to apply the dual damascene process to the formation of copper wiring layers in a semiconductor device required to include a metal-insulator-metal (MIM) capacitor between metal wiring layers, it is necessary to develop a new manufacturing method.
FIGS. 1 and 2
illustrate cross-sectional views of stages of a conventional method for manufacturing a semiconductor device having a MIM capacitor and a damascene wiring layer structure. Referring to
FIG. 1
, a first metal wiring layer
15
and a second metal wiring layer
20
are formed on a lower dielectric layer
10
, which is formed on a semiconductor substrate
1
, such that there is no step difference between the lower dielectric layer
10
and the first and second metal wiring layers
15
and
20
(i.e., top surfaces of the first and second metal wiring layers
15
and
20
are level with a top surface of the lower dielectric layer
10
). Next, a first metal layer is formed on the semiconductor substrate
1
, on which the first and second metal wiring layers
15
and
20
are formed. The first metal layer is patterned, thereby forming a lower electrode
25
of a capacitor to contact the top surface of the second metal wiring layer
20
. Next, a dielectric layer
30
is formed on the semiconductor substrate
1
, on which the lower electrode
25
is formed. Then, a second metal layer is formed on the dielectric layer
30
and then is patterned, thereby forming an upper electrode
35
of a capacitor at a position corresponding to the position of the lower electrode
25
. Next, an interlayer insulating layer
40
is formed on the semiconductor substrate
1
, on which the upper electrode
35
is formed.
Referring to
FIG. 2
, a top surface of the interlayer insulating layer
40
is planarized by chemical mechanical polishing (CMP). Next, the interlayer insulating layer
40
and the dielectric layer
30
are etched, thereby forming a via hole V
1
to expose the top surface of the first metal wiring layer
15
. A first trench T
1
is formed over the via hole V
1
and a second trench T
2
is formed to expose a top surface of the upper electrode
35
. Next, the via hole V
1
and the first and second trenches T
1
and T
2
are filled with copper and then are chemically and mechanically polished, thereby forming a damascene wiring layer structure
45
and a contact plug
50
.
However, such a conventional method has the following problems. First, in the step of patterning the second metal layer to form the upper electrode
35
, the dielectric layer
30
may be damaged by plasma, thereby impairing the performance of a MIM capacitor.
Second, in order to decrease a step difference between the lower electrode
25
and the upper electrode
35
, a step of chemically and mechanically polishing the top surface of the interlayer insulating layer
40
is necessary. In other words, in addition to planarizing the copper filling the via hole V
1
and the first and second trenches T
1
and T
2
by CMP, a step of performing a CMP process on the interlayer insulating layer
40
is also required.
SUMMARY OF THE INVENTION
In an effort to solve the above-described problems, it is a first feature of an embodiment of the present invention to provide a method for manufacturing a semiconductor device having a MIM capacitor and a damascene wiring layer structure without damaging a dielectric layer.
It is a second feature of an embodiment of the present invention to provide a method for manufacturing a semiconductor device having a MIM capacitor and a damascene wiring layer structure without having to perform CMP on an interlayer insulating layer.
Accordingly, to provide the above features, there is provided a method for manufacturing a semiconductor device having a MIM capacitor and a damascene wiring layer structure according to a first embodiment of the present invention, wherein a first metal wiring layer and a second metal wiring layer are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers are level with a top surface of the lower dielectric layer. A first dielectric layer and a second dielectric layer are sequentially formed on the semiconductor substrate on which the first and second metal wiring layers are formed. The first dielectric layer and the second dielectric layer have a hole region through which the top surface of the second metal wiring layer is exposed. An upper electrode of a capacitor is formed by forming a dielectric layer at sidewalls and a bottom of the hole region such that the hole region is completely filled with the upper electrode and a top surface of the upper electrode is level with a top surface of the second dielectric layer. A third dielectric layer and a fourth dielectric layer are sequentially formed on the semiconductor substrate on which the upper electrode is formed. A damascene structure is formed in the fourth, third, second, and first dielectric layers to contact the top surface of the first metal wiring layer, and a contact plug is formed in the fourth and third dielectric layers to contact the top surface of the upper electrode.
Forming the upper electrode of a capacitor may include forming a dielectric layer on the second dielectric layer and at the sidewalls and bottom of the hole region, forming a second metal layer to completely fill the hole region on the semiconductor substrate on which the dielectric layer is formed, and planarizing the semiconductor substrate on which the second metal layer is formed to expose the top surface of the second dielectric layer.
Preferably, the planarization is performed by chemical mechanical polishing (CMP). The second metal layer may be formed of one selected from the group consisting of a Ta layer, a TaN layer, a TaSiN layer, a TiN layer, a TiSiN layer, a WN layer, a WSiN layer, and any combination thereof. Alternatively, the second metal layer may be formed of one selected from the group consisting of a do
Chung Ju-hyuk
Han Ja-Hyung
Park Byung-lyul
Kennedy Jennifer M.
Lee & Sterba, P.C.
Niebling John F.
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