Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-24
2003-11-04
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000
Reexamination Certificate
active
06642093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an embedded DRAM, in which a DRAM (Dynamic Random Access Memory) made up of cells having a CUB (Capacitor Under Bit Line) structure and a logic circuit made up of dual gate salicide CMOS transistors are formed on a same silicon substrate.
2. Background Art
In recent years, semiconductor devices must satisfy various demands: they must be miniaturized and highly integrated having small size and lightweight. Such demands have led to the need for developing a semiconductor device in which various devices are formed on a single chip. In such a representative semiconductor device, a memory device, such as a DRAM, and a logic device are formed on a same semiconductor substrate as a single chip.
Description will be made below of a method for manufacturing a conventional embedded DRAM with reference to
FIGS. 44
to
54
. In
FIGS. 44
to
54
, the left hand side shows the memory cell region, while the right hand side shows the logic circuit region.
First of all, a trench separation oxide film
102
is formed on a semiconductor substrate
101
as shown in FIG.
44
. Then, N-type impurity ions such as phosphorus (P) are implanted in the memory cell region to form the bottom N-well layer (the bottom surface separation layer). After that, the logic circuit region is covered with a photoresist (not shown), and P-type impurities such as boron (B) are implanted in the memory region to form a P-well region. P-type impurities such as boron (B) are also implanted in the logic circuit region, forming a P-well region. Furthermore, an N-well.region (now shown) for forming PMOSs is formed in the logic circuit region.
Then, a gate oxide film
103
is formed by, for example, a thermal oxidation method. After that, a gate electrode (layer) made up of a polycrystalline silicon (layer)
104
and a tungsten silicide (layer)
105
is laminated (on the gate oxide film
103
). Furthermore, a silicon oxide film
106
of TEOS (Tetra Ethyl Ortho Silicate Glass), etc. and a silicon nitride film
107
are laminated on the gate electrode (layer). The silicon oxide film
106
and the silicon nitride film
107
are used as etching masks for forming gate electrodes and as etching stoppers for forming self alignment contacts disposed between the gate electrodes. After that, impurities are implanted in the semiconductor substrate
101
, forming the source/drain regions
108
a
and
109
a
of the transistors.
Then, as shown in
FIG. 45
, a silicon nitride film is formed, and anisotropic etching is carried out, forming sidewall spacer silicon nitride films
110
on the gate electrode sidewalls. Then, in the logic circuit region, impurities are implanted over the sidewall spacer silicon nitride films
110
to form the source/drain regions
109
b
, thereby forming a LDD (Lightly Doped Drain) structure.
Then, as shown in
FIG. 46
, an interlayer insulation film
111
of BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate Glass), etc. is laminated on a thin silicon nitride film (not shown) disposed on the surface. Contact holes are then formed between the gate electrodes in the memory cell region by the self-alignment contact (hereinafter referred to as SAC) method, and filled with polycrystalline silicon, thereby forming a polycrystalline silicon plug
112
.
An interlayer insulation film
113
of TEOS, etc. is then formed on the interlayer insulation film
111
as shown in FIG.
47
. After that, in the logic region, contact holes reaching the source/drain regions
109
are formed, and filled with a film
114
made of titanium nitride and tungsten. The film
114
(contact holes) is patterned to form bit line contacts. Likewise, bit line contacts (not shown) reaching the polycrystalline silicon plug
112
are formed in the memory cell region.
Then, as shown in
FIG. 48
, after an interlayer insulation film
115
of TEOS, etc. is formed, holes reaching a portion of the polycrystalline silicon plug
112
are formed and filled with silicon nitride film sidewall spacers
116
and polycrystalline silicon
117
, thereby forming storage node contacts
118
.
Then, as shown in
FIG. 49
, an interlayer insulation film
120
of BPTEOS, etc. is laminated on a silicon nitride film
119
disposed on the surface, and subjected to CMP for planarization. The silicon nitride film
119
is used as etching stoppers. Cylindrical capacitor openings
121
reaching portions of the storage node contacts
118
are formed. The formation process is set such that the first etching stops at the surface of the silicon nitride film
119
, and the second etching forms the openings in the silicon nitride film
119
.
After that, as shown in
FIG. 50
, a polycrystalline silicon film is formed on the main surface including the surfaces of the cylindrical capacitor openings
121
and subjected to surface roughening treatment to increase its surface area. The cylindrical capacitor openings
121
are then covered with a photoresist, and the polycrystalline silicon (film) is subjected to anisotropic etching so as to leave the polycrystalline silicon only inside the cylindrical capacitor openings
121
. This completes the formation of capacitor bottom electrodes
122
.
Furthermore, tantalum pentoxide (not shown), for example, is formed on the main surface including the surfaces of the cylindrical capacitor openings
121
as a capacitor dielectric film, as shown in FIG.
51
. Then, a film containing titanium nitride is formed and patterned by use of a photoresist, thereby forming capacitor top electrodes
123
.
Then, as shown in
FIG. 52
, an interlayer insulation film
124
of plasma TEOS, etc. is formed on the capacitor top electrodes
123
. Subsequently, in the logic circuit region, contact holes
125
are formed to expose the surfaces of the bit line contacts
114
.
The contact holes
125
are then filled with titanium nitride
126
and tungsten
127
, acting as barrier metals, as shown in FIG.
53
.
Then, as shown in
FIG. 54
, aluminum wires
129
sandwiched by films of titanium
128
a
and
128
b
are formed on the contact holes.
This completes description of a method for manufacturing a semiconductor device formed by use of a conventional technique.
Description will be made below of a problem with the above conventional technique with reference to FIG.
54
. Since the cell area of DRAMs has been significantly reduced in recent years, self alignment contact holes produced using the silicon nitride film
107
as their etching stoppers have been employed as the contact holes disposed between the gate electrodes in the memory cell region. In this case, the tops of the gate electrodes are covered with the silicon nitride film
107
, etc. This means that the silicon nitride film
107
is also formed in the logic region, making it difficult to form cobalt silicide on the gate electrodes for the purpose of forming highly-integrated and high-performance MOS transistors in the logic circuit region.
To cope with the above problem, the gate electrodes currently have a layered structure made up of the polycrystalline silicon (layer)
104
and the tungsten silicide (layer)
105
in order to reduce the resistance. However, this structure still has a high resistance value as compared with the case where cobalt silicide is formed on the gate electrodes, preventing formation of highly-integrated and high-performance MOS transistors in the logic circuit region.
The present invention has been devised to solve the above problem and is applied to embedded DRAMs which reqire memory cells and highly-integrated and high-performance logic transistors. It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device, in which the gate electrodes and the source/drain regions of the CMOS transistors in the logic region can be “cobalt-silicified”.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, in a method for manufacturing a semi
Amoo Atsushi
Kubo Shunji
Dang Phuc T.
Mitsubishi Denki & Kabushiki Kaisha
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