Method for manufacturing a semiconductor device

Details Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device

2001-09-17

2003-07-22

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S611000, C257S781000, C257S638000

Reexamination Certificate

active

06596633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a structure of coating an edge of a connection hole of a metal pattern layer among plural metal pattern layers with a passivation layer, the metal pattern layer which will be a chip pad, and a method for manufacturing the same.
2. Description of the Related Arts
Semiconductor devices are fabricated on a silicon substrate using successive steps of photolithography, etching, diffusion, and deposition.
A deposition step refers to a kind of the material synthesis process, in which a desired thin layer is obtained by changing a specific element or compound from the source in a gas or vapor phase into a solid phase. In the manufacturing of the semiconductor device, thin layers of silicon oxide, silicon nitride, various metals and/or silicide are required. All the thin layers are obtained by the deposition step.
The deposition step is also referred to as a thin film formation process, and is divided includes two methods, that is, a PVD (Physical Vapor Deposition) and a CVD (Chemical Vapor Deposition). The physical vapor deposition is a deposition method, in which a desired thin layer is deposited only by changing a phase of the source, without adding or omitting other components to or from the source. On the other hand, chemical vapor deposition includes the chemical reactions, so there are differences in a physical and a chemical structure between the kind of source and the deposited product. Generally, a sputtering method is used for the physical vapor deposition.
Among the above-described deposition steps, a metallization step means a metal wiring step, in which aluminum (Al) with the thickness of about 6,000 Å is deposited on the silicon substrate to electrically interconnect a plurality of the semiconductor devices formed on the upper surface of the silicon substrate to each other, and to form chip pads for electrically connecting the semiconductor devices to external circuitry.
A method for manufacturing a semiconductor device using a conventional deposition step will be described hereinafter, with reference to FIG.
1
through FIG.
4
.
FIG. 1
schematically shows a coating of a passivation layer
17
on an upper surface of a silicon substrate
10
, where a plurality of metal pattern layers
12
,
14
are formed, in order to manufacture a plurality of semiconductor devices (
30
in
FIG. 4
) on the silicon substrate
10
, and
FIG. 2
is a cross-sectional view taken along the line
2
—
2
in FIG.
1
. With reference to FIG.
1
and
FIG. 2
, a first metal pattern layer
12
is deposited on the upper surface of the silicon substrate
10
. And, the first metal pattern layer
12
is electrically insulated from a second metal pattern layer
14
by interposing an inter metal dielectric
16
(IMD) between the first metal pattern layer
12
and the second metal pattern layer
14
. To electrically interconnect the first metal pattern layer
12
to the second metal pattern layer
14
, a connection hole
15
is formed by selectively removing the inter metal dielectric
16
on a designated portion. A designated portion of the second metal pattern layer
14
is used as a chip pad (
19
in FIG.
4
). The upper surface of the silicon substrate including an upper surface of the second metal pattern layer
14
is coated with the passivation layer
17
.
Herein, the first metal pattern layer
12
is formed by successively depositing a Ti/TiN layer
12
b
, an Al layer
12
a
, and a TiN layer
12
c
on the upper surface of the silicon substrate
10
. The second metal pattern layer
14
is formed by successively depositing a Ti layer
14
b
and an Al layer
14
a
on an upper surface of the Al layer
12
a
of the first metal pattern layer
12
. Generally, all the layers are deposited by sputtering. The TiN layer
12
c
of the first metal pattern layer
12
is positioned between the lower surface of the inter metal dielectric
16
and the upper surface of the Al layer
12
a
of the first metal pattern layer
12
, and the Ti/TiN layer
12
b
of the first metal pattern layer
12
is used as a barrier metal layer.
The connection hole
15
is formed by selectively removing a portion of the inter metal dielectric
16
after depositing the first metal pattern layer
12
and the inter metal dielectric
16
on the silicon substrate
10
. Consequently, the upper surface of the silicon substrate
10
including the first metal pattern layer
12
and the inter metal dielectric
16
is uneven and stepwise. Therefore, the second metal pattern layer
14
deposited on the upper surfaces of the first metal pattern layer
12
and the inter metal dielectric
16
, is formed with the uneven thickness. Described in more detail, a concave corner
14
c
is formed along an edge
13
, where the first metal pattern layer
12
is in contact with the inter metal dielectric
16
, in which the second metal is thinner in the thickness than that of any other portion of the second metal pattern layer
14
. Accordingly, the concave corner
14
c
having a bad step coverage is formed on the edge
13
, where the first metal pattern layer
12
is in contact with the inter metal dielectric
16
.
The reason that the concave corner
14
c
is formed on the second metal pattern layer
14
will be described hereinafter. The second metal pattern layer
14
is deposited on the upper surfaces of the first metal pattern layer
12
including the connection hole
15
, and the inter metal dielectric
16
by sputtering. In sputtering, Ar atoms are accelerated and collide with a target in the vacuum condition. In the present invention, the target is made of an Al (Aluminum) and a Ti (Titanium) plate. Molecules of the target material are broken off by the colliding of the Ar atoms and deposited on the upper surface of the silicon substrate
10
. At this time, the number of the particles of the components of the target, which is deposited on the vertical surface of the silicon substrate
10
to the target, is fewer than that of the components, which is deposited on the horizontal surface of the silicon substrate
10
to the target. Particularly, the number of the particles of target material deposited on the edge
13
, on which the first metal pattern layer
12
is in contact with the inter metal dielectric
16
, is fewer than that of the target material deposited on any other portion of the silicon substrate
10
. As described above, since the number of the particles of target material deposited on the edge
13
is fewest, the concave corner
14
c
of the second metal pattern layer
14
is indented toward the edge
13
.
The passivation layer
17
is composed of PEOX (Plasma Enhanced silicon Oxide) and silicon nitride (Si3N4). Reference numeral
17
a
refers to a point or boundary for etching the passivation layer
17
to expose a portion of the second metal pattern layer
14
to the outside, the portion which will be a chip pad (
19
in FIG.
4
), that is, the chip pad portion of the second metal pattern layer
14
. The etched point
17
a
is disposed along an outer periphery of the connection hole
15
.
Then, a photo-etching step is carried out for removing a portion of the passivation layer
17
on the upper surface of the second metal pattern layer
14
to expose the chip pad portion of the second metal pattern layer
14
to the outside. As shown in
FIG. 3
, an upper surface of the passivation layer
17
is coated with a photoresist
18
and a developing step is carried out for removing the photoresist
18
of the upper surface of the chip to expose the pad portion of the second metal pattern layer
14
. After that, as shown in
FIG. 4
, a portion of the passivation layer
17
is removed from the upper surface of the chip pad portion of the second metal pattern layer
14
by the dry etching method, and an ashing/strip step is carried out for removing the photoresist
18
remaining on the silicon substrate
10
. Accordingly, a semic

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