Method for manufacturing a semiconductor device

Details Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device

2000-06-28

2003-03-11

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S253000, C438S254000, C438S396000, C438S397000

Reexamination Certificate

active

06531362

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device; and, more particularly, to an improved method for manufacturing a semiconductor device incorporating therein an insulating layer for preventing metal patterns from bridging therebetween.
DESCRIPTION OF THE PRIOR ART
In recent years, as a dynamic random access memory (DRAM) is integrated more and more to a higher level, a size of cell tends to be further reduced. However, to improve endurance against a soft error, the capacitor must secure a certain area on a silicon substrate.
A cylindrical capacitor with a three-dimensional structure has been introduced to solve the problem.
In
FIGS. 1A and 1B
, there is illustrated a prior art method for manufacturing a semiconductor device having a plurality of cylindrical capacitors at a cell region
24
of a silicon substrate
2
. In the beginning, after a multiple number of gates
6
and a plurality of junctions
4
are formed in the cell region
24
of the silicon substrate
2
. Thereafter, the cylindrical capacitors are electrically connected to the junction
4
through a plurality of plugs
10
, respectively. Each cylindrical capacitor has a lower electrode
12
, a side wall
14
formed around the lower electrode
12
, a dielectric layer
16
formed on top of the lower electrode
12
and a upper electrode
18
formed on top of the dielectric layer
16
. In the next step, a borophosphosilicate glass (BPSG) layer
20
is deposited on top of the upper electrode
18
of the cylindrical capacitors and a peripheral region
26
of the silicon substrate
2
. In general, the BPSG layer
20
is used as an insulating layer interlayered between metal patterns. The BPSG layer
20
is reflowed to planarize the surface thereof. And then, a photoresist layer
22
is formed on top of the BPSG layer
20
of the peripheral region
26
, as shown in FIG.
1
A.
In order to further smooth a step contour between the cell region
24
and the peripheral region
26
, a portion
27
of the BPSG layer
20
must be etched back to a desired thickness, wherein the desired thickness is represented as a dot line in FIG.
1
A.
A polysilicon plug
28
is formed on top of the BPSG layer
20
at the peripheral region
26
. Finally, a redundancy word line
30
is formed on top of the planarized BPSG layer
20
with extending to the polysilicon plug
28
.
There are certain deficiencies associated with the above-described method for manufacturing the semiconductor device during the planarizing process. For example, it is difficult to etch the portion
27
of the BPSG layer
20
without exposing an edge portion
32
of the upper electrode
18
, because a thickness of the BPSG layer
20
at the edge portion
32
is smaller than that of the portion
27
on top of the plug
10
. In this result, a bridge is frequently occurred between the edge portion
32
of the upper electrode
18
and the redundancy word line
30
, which, in turn, degrades the overall performance of the semiconductor device.


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Wolf et al. “Silicon Processing for the VLSI Era, vol. 1—Process Technology”, Lattice Press, 1986, pp. 529-535, and 539-542.

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