Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-12
2001-08-14
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S382000, C438S210000
Reexamination Certificate
active
06274422
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to semiconductor device having a resistance element used in a circuit thereof and manufacturing method thereof.
2. Description of the Related Art
Conventionally, when a resistance value required in a resistance element used in a circuit of a semiconductor device is as great as some hundreds k&OHgr; or more, an N-type diffusion layer formed on a surface of a P-type semiconductor substrate or a P-type diffusion layer formed on a surface of an N-type semiconductor substrate is used as the resistance element. These N-type and P-type diffusion layers are manufactured in the same manufacturing step and has the same structure as those of a source or a drain of an MOS transistor formed on the same semiconductor substrate.
There is a method for utilizing an N-well which is a substrate electrode of a P-type MOS transistor as a resistance element having high resistance (which will be referred to as “N-well resistance, hereinafter).
FIGS. 1A
to
1
D are sectional views showing the conventional manufacturing method of the N-well resistance in the order of manufacturing steps.
First, as shown in
FIG. 1A
, portions which will become element separation regions on a surface of a P-type semiconductor substrate
32
are selectively oxidized to form LOCOS oxide films
31
. Portions in which the LOCOS oxide film
31
is not formed become diffusion layer regions
33
.
Next, as shown in
FIG. 1B
, portions which will become N-well and N-well resistance for a P-type MOS transistor region are selectively subjected to ion implantation of phosphorus with energy of 400 KeV, for example, thereby forming N-well
35
and N-well resistance
34
.
Next, as shown in
FIG. 1C
, portions of the surface of the P-type semiconductor substrate
32
which will become P-well for an N-type MOS transistor region are selectively subjected to ion implantation of boron with energy of 400 KeV, for example, thereby forming P-well
36
.
Then, as shown in
FIG. 1D
, gate polysilicon
37
of the MOS transistor is formed and then, P-type MOS transistor portions are selectively subjected to ion implantation of boron, thereby forming P-type diffusion layers
39
to provide the P-type MOS transistor
41
. Next, the N-type MOS transistor portions are selectively subjected to ion implantation of arsenic, thereby forming N-type diffusion layers
40
to provide the N-type MOS transistor
42
. Simultaneously, N-well resistance portions are also selectively subjected to ion implantation of arsenic, thereby forming N-type diffusion layers
38
which will become contact portions for wirings of the N-well resistance
34
.
However, in recent years, efforts have been made to reduce the resistance value of the diffusion layer portions forming a source or a drain so as to enhance the performance of MOS transistor. As a result, the resistance value of the diffusion layer formed on a surface of a semiconductor substrate is reduced as low as about one-tenth, and the area required to form a resistance element having the same resistance value as that of the conventional element using the diffusion layer is adversely increased as much as ten times.
Further, when the N-well resistance is utilized, dimensional precision when the N-well resistance is formed is extremely inferior to that when the diffusion layer is formed, and if attempt is made to obtain a predetermined resistance value while keeping the precision in some degree, it is necessary to prepare N-well resistance having wide area, which can be a cause to adversely influence the integrated degree of a semiconductor integrated circuit.
FIG. 2
is a plan view of one example of layout when a resistance of 100 k&OHgr; is formed using a conventional N-well resistance. Here, the resistance value of N-well resistance
51
is 700 k&OHgr;, width of the N-well resistance is 5 micron, a distance between adjacent N-well resistances is 3 micron. Since the N-well resistance
51
is formed simultaneously with manufacturing steps of the P-type MOS transistor and the N-type MOS transistor as described above, the N-well resistance
51
can not be formed in a region where the MOS transistor is formed in a superposing manner. Therefore, a region for the N-well resistance is set separately from the MOS transistor region, and ten N-well resistance
51
each having the length of 71.5 micron and the width of 5 micron are connected to one another in series by aluminum wirings
52
, thereby realizing the resistance of 100 k&OHgr;. The region required for the layout of this N-well resistance is as large as about 71.5 micron in the lateral direction and 79 micron in the vertical direction.
As described above, it is necessary to set a region for forming the conventional N-well resistance separately from the MOS transistor region, which adversely influences the integrated degree of a semiconductor integrated circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof using a resistance element which does not adversely influence the integrated degree of a semiconductor integrated circuit.
A semiconductor device according to the present invention, comprises: a first conductive type well layer formed on a surface of the semiconductor substrate; a second conductive type impurity diffusion layer having source/drain of MOS transistor formed on a surface of the first conductive type well layer and is the opposite conductive type; a second conductive type well layer formed below the first conductive type well layer; and terminals consist of second conductive type well layers formed on opposite ends of the second conductive type well layer such as to respectively reach the surface of the semiconductor substrate.
A manufacturing method of a semiconductor device according to the invention, comprises the steps of: forming a element separating oxidation film on a surface of a first conductive type semiconductor substrate; forming a second conductive type well layer having the conductive type opposite from the first conductive type in the deep portion, in the first conductive type semiconductor substrate by ion implantation; forming terminals on opposite ends of the second conductive type well layer such as to respectively break through the surface of the first conductive type semiconductor substrate; forming a first conductive type well layer on the surface of the first conductive type semiconductor substrate above the second conductive type well layer; and forming a second conductive type impurity diffusion layer on a surface of the first conductive type well layer.
With the above structure, a resistance element can be formed in superposed manner below an MOS transistor formed on the surface of the first conductive type semiconductor substrate. Therefore, it is possible to enhance the integrated degree of a semiconductor integrated circuit.
It is preferable that the second conductive type resistance well layer is formed by subjecting a first conductive type semiconductor substrate to ion implantation with 800 keV using phosphorus as impurity.
In the semiconductor device of the invention, the second conductive type resistance well layer is formed in the deep portion in the first conductive type semiconductor substrate, and the first conductive type MOS transistor is formed above the second conductive type resistance well layer. Therefore, it is unnecessary to set a formation region for the MOS transistor region separately from the N-well resistance unlike the conventional resistance using the well layer, and it is possible to enhance the integrated degree of a semiconductor integrated circuit.
REFERENCES:
patent: 4228450 (1980-10-01), Anantha et al.
patent: 5319236 (1994-06-01), Fujihira
patent: 5679593 (1997-10-01), Miller, Jr. et al.
patent: 5880001 (1999-03-01), Camenzind
patent: 6100153 (2000-08-01), Nowak et al.
patent: 6137664 (2000-10-01), Casper et al.
patent: 56-37645 (1981-
Hayes Soloway Hennessey Grossman & Hage PC
NEC Corporation
Nguyen Tuan H.
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