Method for manufacturing a semiconductor device

Details Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device

1985-03-19

1986-04-22

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576B, 29580, 156643, 156646, 156647, 156651, 156657, 156662, 252 795, 357 34, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

045840555

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
This invention relates to a method for manufacturing various kinds of discrete semiconductor devices or a semiconductor device such as a semiconductor integrated circuit device and so on.
2. Background Art
Upon manufacturing various kinds of semiconductor devices, there is frequently employed such a process for selectively etching a semiconductor layer such as a polycrystalline semiconductor layer or amorphous semiconductor layer.
With reference to FIGS. 1 to 9, an example of a prior art method for manufacturing a semiconductor device by forming a polycrystalline silicon semiconductor layer on a silicon substrate and then selectively etching the same will be described. In this example, an NPN-type bipolar transistor is obtained.
At first, as shown in FIG. 1, there is prepared a P-type single crystalline silicon substrate 1 and an N-type buried region 2 is formed on a main surface 1a thereof by a selective diffusion process or the like.
As shown in FIG. 2, an N-type silicon semiconductor layer 3 is epitaxially grown on the whole of the main surface 1a of the substrate 1 to thereby form a single crystalline silicon substrate 4.
As shown in FIG. 3, a thick oxide insulating layer 5 is formed in the silicon semiconductor layer 3 of the substrate 4 by a selective-thermal-oxidizing the same except portions 3a and 3b in which an emitter or base region and a collector deriving electrode are to be formed respectively on the buried layer 2.
As shown in FIG. 4, on the semiconductor layer 3 including the oxide insulating layer 5, there is thoroughly formed a P-type impurity, for example, boron B doped polycrystalline silicon semiconductor layer 6 by a chemical vapor deposition method (CVD method) and this polycrystalline silicon semiconductor layer is patterned by selectively etching other portions except the portions which will finally become a base electrode derive region and a base electrode, for example. Then, on the whole surface including the polycrystalline silicon semiconductor layer 6, there is formed an oxide mask layer 7 of an SiO.sub.2 similarly by, for example, the CVD method.
As shown in FIG. 5, the photolithography is carried out for the mask layer 7 to selectively form a window 7a through a part thereof on the portion 3a of the semiconductor layer 3, particularly a portion on which the emitter region will be formed finally and the polycrystalline silicon layer 6 is selectively etched out through the window 7a so as to form a window 6a therethrough corresponding to the window 7a.
As shown in FIG. 6, using the polycrystalline silicon layer 6 and the mask layer 7 thereon as a mask, a P-type impurity-doped region 8 is formed by selectively ion-implanting a P-type impurity, for example, boron B into the portion 3a of the semiconductor layer 3 through the windows 7a and 6a.
As shown in FIG. 7, an SiO.sub.2 oxide insulating layer 9 is formed thoroughly on the mask layer including the region 8 so as to close the window 7a by the CVD method or the like. Further, the ion-implanted region 8 is activated by the annealing so as to become a base region, and a high concentration region 8a for use in deriving the base electrode is formed, for example, around the base region 8 by diffusing the impurities to the portion 3a from the impurity-doped polycrystalline silicon layer 6 deposited directly on the portion 3a.
As shown in FIG. 8, a window 9a is formed through a part of the region 8 by the photolithography of the oxide insulating layer 9 and a window 10 is formed on the other portion 3b of the semiconductor layer 3 by selectively etching the oxide insulating layer 9 and the mask layer 7 formed beneath the oxide insulating layer so as to expose the portion 3b to the outside. Then, an emitter region 11 and a low resistance region 12 for use in deriving a collector electrode are respectively formed by, for example, ion-implanting N-type impurity through these windows 9a and 10.
As shown in FIG. 9, a window 13 is formed on a part of the polycrystalline silicon layer 6 contacting with the b

REFERENCES:
patent: 4433470 (1984-02-01), Kaneyama et al.
patent: 4481706 (1984-11-01), Roche
patent: 4522682 (1985-06-01), Soclof

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