Method for manufacturing a semiconductor device

Details Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device

1996-09-20

1999-11-16

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438970, 438738, H01L 218247

Patent

active

059857161

ABSTRACT:
A polysilicon layer 38 located upward of a local oxidation of silicon (LOCOS) layer 20 is removed partially when selective etching of the polysilicon layer 38 for forming a floating gate FG is carried out by carrying out anisotropic etching. The etching is stopped when only the polysilicon layer 38 is removed. Wet-etching usually carried out at the final phase of the anisotropic etching process is not performed. In this way, the LOCOS layer 20 located underneath the polysilicon layer 38 is not over-etched. As a result, an inter layer 34 is not formed in a shape of eaves on the LOCOS layer 20 when the inter layer 34 is formed. Therefore, the probability of causing stringers underneath the inter layer 34 is remarkably low.

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patent: 5070032 (1991-12-01), Yuan et al.
patent: 5087584 (1992-02-01), Wada et al.
patent: 5336628 (1994-08-01), Hartmann
patent: 5607868 (1997-03-01), Chida et al.
patent: 5656527 (1997-08-01), Choi et al.
patent: 5686333 (1997-11-01), Sato
patent: 5789294 (1998-08-01), Choi

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