Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-08-22
2006-08-22
Chaudhrai, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S589000
Reexamination Certificate
active
07094644
ABSTRACT:
The present invention discloses a method for manufacturing a flash memory cell by using a trench method which can eliminate an increase of a stepped portion in a flash process as compared to a logic process by forming a floating gate on a STI portion since the floating gate is added to the flash memory as compared to a logic process. The method comprises the steps of: forming a plurality of trenches on both sides of the center of a silicon substrate; forming a trench isolation by filling the trenches with an insulating material; controlling a bonding ratio between floating gates by controlling the width and depth of the trench isolation at the both sides of the silicon where a tunnel oxide film grows within one cell; depositing a tunnel oxide film and then performing a well formation and a threshold voltage ion implantation; forming a floating gate within the trench isolations by depositing a floating gate polysilicon and then patterning the same into a predetermined shape; sequentially forming an ONO layer and a control gate poly on the patterned floating gates; and forming a control gate by sequentially etching the control gate poly and the ONO layer.
REFERENCES:
patent: 6221718 (2001-04-01), Hong
patent: 6413809 (2002-07-01), Nakamura et al.
patent: 6531733 (2003-03-01), Jang
patent: 6642108 (2003-11-01), Lee et al.
patent: 6682977 (2004-01-01), Chang
Chaudhrai Chandra
Marshall & Gerstein & Borun LLP
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