Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-12-27
2004-10-26
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C438S692000, C438S697000, C438S700000
Reexamination Certificate
active
06809031
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the chemical mechanical polishing (CMP) of substrates, and more particularly, to techniques for manufacturing a reclaimable test pattern wafer to be used in CMP applications.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and substrate cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed over and into silicon substrates. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level there is a need to planarize metal or associated dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization, e.g., such as copper.
As transistor device structures become smaller and more complex, the precision required of CMP equipment increases. The CMP industry continues to meet demands with an ever-expanding body of technology and implementation to produce more precise and refined tools. All CMP tools are continually tested and calibrated, or characterized, to evaluate performance of a tool as well as various abrasive and fabrication material properties, and methods of use. By way of example, characterization can include the measurement of rate of removal using a plurality of slurries or different polishing surfaces. Further, characterization includes measurement of removal rates for disparate materials such a oxides and metals to determine or predict end points of processing. The characterization is typically done with a “test” wafer. A test wafer is usually one of a blanket film or a test pattern wafer. Using a test wafer, a CMP tool is used to process a substrate in the same manner as in the actual fabrication of a semiconductor wafer. During the characterization operation, the process, materials, tool, and the like are evaluated, measured, and modified to achieve more precise control of the CMP process.
A test pattern wafer is fabricated in much the same manner as a production wafer. In order to accurately characterize the CMP process, the test pattern wafer must present the same or similar structures, the structures must be constructed of essentially the same materials, and the structures must be in the same or similar geometric arrangements as those of production wafers.
FIG. 1
shows a cross section of a typical prior art test pattern wafer
10
used in CMP applications.
FIG. 1
shows a test pattern wafer
10
that replicates a shallow trench isolation (STI) structure. A silicon wafer
12
is etched to create trenches
15
in the silicon. A pad oxide layer
14
is fabricated over the silicon wafer
12
, and a silicon nitride (SiN) layer is fabricated over the pad oxide layer
18
to form a simulated gate, or gate-type structure. In one embodiment, even the source/drain regions
18
are created in the simulated gate structure. Finally, a high density plasma (HDP) fill
20
is deposited over the entire structure just as in the fabrication of a production wafer. The HDP fill is then removed by CMP to expose a SiN film which is protecting the surface of the gate structure, leaving the trench
15
filled to create the basic STI structure.
It should be appreciated that a test wafer structure in the illustrated example is processed in essentially the same manner as a production wafer. The test pattern wafer is etched to define the STI and gate structures, pad oxide and SiN layers are fabricated, and the structure is deposited with HDP oxide fill.
FIG. 1
illustrates a typical single structure used in CMP characterization. A test pattern wafer typically contains a plurality of dies or simulated microchip structures that vary in complexity and density from low density concentration of the structures to very high density concentration of structures across a single test wafer. Once the CMP characterization test of the wafer is completed, the wafer, no longer useful for production or test purposes, is scrapped.
The silicon used for wafers in semiconductor manufacture is plentiful, but it is not inexpensive. Production wafers result in a plurality of microchip devices and generate a large return on the investment of time and material. Test wafers, on the other hand, do not result in structures generating monetary return, but require essentially the same investment of time and material to create the precise structures used in CMP characterization. Test pattern wafer structures such as that illustrated in
FIG. 1
require etching of the silicon substrate, a complex, precision operation. Test pattern wafers further require multiple fabrication steps to create a plurality of structures in increasing densities on the surface of the silicon substrate. Test pattern wafers are therefore expensive to produce, expensive to procure, and are scrapped after a single use. There is little incentive for the production of test pattern wafers with such limited utility and return, but there remains a constant demand for test pattern wafers by semiconductor fabrication equipment manufacturers, as well as manufacturers of semiconductors using CMP tools. The constant demand results in an ever-increasing cost for test pattern wafers from dwindling numbers of suppliers.
What is needed is a method for manufacturing a reclaimable test pattern wafer for CMP applications. The method should include a way to fabricate a test pattern wafer that is suitable for CMP characterization, and then can be reclaimed to create another test wafer for another CMP characterization.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a method for manufacturing a test pattern wafer to be used to characterize CMP processes. The test pattern wafer includes a sacrificial oxide layer over a silicon substrate enabling the fabrication of test pattern structures in and over the sacrificial oxide which is easily etched and otherwise fabricated, and then easily removed from the silicon substrate following the CMP characterization. In this manner, the sacrificial oxide layer preserves the structure and integrity of the silicon substrate, and provides for reclaiming the substrate for subsequent test pattern wafer fabrication. The present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Exemplary embodiments of the present invention are described below.
In accordance with one aspect of the invention, a method for fabricating a test pattern wafer to be used in CMP characterization operations is provided. The method includes providing a silicon substrate and then depositing a layer of oxide over a surface of the substrate. The method further provides for defining a test pattern structure and then fabricating the test pattern structure over the layer of oxide. The method then includes characterizing a CMP process using the test pattern wafer, and then removing the test pattern structure and layer of oxide layer from the silicon substrate.
In accordance with another aspect of the invention, a method is provided for reclaiming a silicon substrate for repeated chemical mechanical polishing characterization. The method includes forming a sacrificial oxide layer over the silicon substrate and then forming test features in the sacrificial oxide layer. Chemical mechanical polishing characterization is performed using the test features which provides data regarding chemical mechanical polishing p
Lam Research Corporation
Martine & Penilla LLP
Tran Binh X.
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