Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-02-02
2001-10-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S266000, C438S267000
Reexamination Certificate
active
06303438
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and a semiconductor integrated circuit.
In recent years, a highly integrated semiconductor memory device (memory LSI) has been increasingly demanded to operate at a higher rate with reduced power consumption. As a highly integrated semiconductor memory device which can electrically write and erase data, a flash EEPROM (electrically erasable programmable read only memory) has been widely used.
FIG. 14D
shows the cross section of a conventional flash EEPROM. The flash EEPROM will be described with reference to the method for fabricating the same.
First, as shown in
FIG. 14A
, after a gate oxide film
102
has been formed by oxidizing the surface of a semiconductor substrate
101
, a poly-silicon film
130
including a portion to be a floating gate
103
is deposited thereon. Next, a silicon nitride film
131
is deposited on the poly-silicon film
130
, and an opening is provided through a region defining the position and the shape of the floating gate
103
by performing a commonly used photolithography process on the silicon nitride film
131
. Next, the exposed surface of the poly-silicon film
130
is selectively oxidized by using the silicon nitride film
131
having such an opening as a mask, thereby forming an oxide film
104
on the poly-silicon film
130
.
Next, after the silicon nitride film
131
has been removed, the poly-silicon film
130
is patterned, thereby forming the floating gate
103
as shown in FIG.
14
B. The oxide film
104
is formed on the floating gate
103
. The film thickness of the peripheral region of the floating gate
103
becomes larger than that of the center region thereof. In other words, the floating gate
103
has a sharpened peripheral region, which shape is affected by a Bird's Peak generated by the formation of the oxide film
104
.
Subsequently, as shown in
FIG. 14C
, the sides of the floating gate
103
are oxidized, thereby forming a second gate oxide film
107
. Thereafter, a control gate
109
is formed so as to overlap the floating gate
103
.
Finally, as shown in
FIG. 14D
, impurity ions are implanted into the substrate
101
, thereby forming a drain region
112
and a source region
113
.
The write of data is performed by accelerating the electrons from the source region
113
by a high electric field formed between the floating gate
103
and the control gate
109
and by injecting the electrons into the floating gate
103
. The erasure of data is performed by taking out the electrons, which have been accumulated in the floating gate
103
, from the floating gate
103
into the control gate
109
upon the application of a positive voltage to the control gate
109
. Since the peripheral region of the floating gate
103
has a sharpened shape as described above, the electric field is concentrated in the peripheral region. Thus, the electrons can be taken out more easily.
However, the above-described structure has the following problems.
First, the flash EEPROM has a problem in that the data write speed thereof is lower than that of a DRAM by two orders of magnitude. Such a low data write speed necessarily requires increasing the voltages (i.e., a drain voltage and a gate voltage) for writing data. As a result, the circuit configuration and the fabrication process thereof are complicated. In other words, it is very difficult to improve both a write speed and write voltages. This is because, in order to increase such a very low write speed, there is no other means than setting the voltages at high values. For example, when a control gate voltage is set at about 9 V and a drain voltage is set at about 4.5 V for writing data, a write time, required for varying an inverted voltage necessary for reading, should be at least as long as 10 &mgr;s.
One of the reasons for such a long write time is poor efficiency with which channel hot electrons are injected into the floating gate. In writing data, in a conventional flash EEPROM, the channel hot electrons are scattered to be oriented in all the directions. However, since an electric field is applied in the direction from the source toward the drain, the velocities of the channel hot electrons are accelerated in this direction. Since the floating gate is not located in this direction of the velocity vectors of the channel hot electrons, the resulting injection efficiency and the resulting write efficiency are far from being satisfactory. Consequently, it has been impossible to meet the demand for increasing a write speed and for decreasing write voltages.
In addition, the device shown in
FIG. 14D
increases data erasure (electron takeout) efficiency by sharpening the peripheral region of the floating gate
103
. According to such a method, the efficiency is surely increased, but the region, from which the electrons are taken out, is adversely restricted to a narrow area. As a result, the current density is undesirably increased in such an area and the oxide film is more likely to be damaged.
Furthermore, in the prior art, if a mask cannot be satisfactorily aligned with the control gate
109
during the patterning of the control gate
109
, then the positional relationship between the control gate
109
and the floating gate
103
is varied. As a result, an effective channel length cannot be precisely defined, thereby causing a large variation in resulting electric characteristics.
SUMMARY OF THE INVENTION
The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and a second gate insulating film portion formed in the step side region and the second surface region. The control gate is formed on the first gate insulating film portion. A part of the floating gate faces the step side region via the second gate insulating film portion, and another part of the floating gate is adjacent to the control gate via the second insulating film.
A method for fabricating the nonvolatile semiconductor memory device of the present invention includes the steps of: forming an insulating film including a portion functioning as a first gate insulating film on a semiconductor substrate; forming a control gate on the portion of the insulating film functioning as the first gate insulating film; forming a capacitive insulating film on surfaces of the control gate; covering the capacitive insulating film, which is located on sides of the control gate, with side walls; partially etching the insulating film and a surface of the semiconductor substrate by using the control gate and the side walls as a mask, thereby forming a concave portion in the surface of the semiconductor substrate; forming a second gate insulating film in the concave portion; selectively removing the side walls; and forming a floating gate having a surface facing one of the sides of the control gate via the capacitive insulating film and having a surface facing a side of the concave portion of the semiconductor substrate via the second gate insulating film.
Another alternative method for fabricating the nonvolatile semiconductor memory device of the present invention includes the steps of: forming an insulating film including a portion functioning as a first gat
Hori Atsushi
Kato Jun-ichi
Odanaka Shinji
Ogura Seiki
Bowers Charles
Chen Jack
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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