Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-14
2002-09-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000, C438S302000
Reexamination Certificate
active
06444525
ABSTRACT:
The present invention claims the benefit of Korean Patent Application No. P2000-67718 filed in Korea on Nov. 15, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory, and more particularly, to a method for manufacturing a nonvolatile memory.
Background of the Related Art
In general, semiconductor memories, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), and a read only memory (RAM), for example, have been widely used. The DRAM is most widely used due to the spread of personal computers. The DRAM commands more than 80% of the semiconductor memory market.
Presently, nonvolatile memories have begun to substitute for DRAM memories. In several years, nonvolatile memories, such as flash and electrically erasable programmable ROM (EEPROM), for example, may substitute for the DRAM memory. However, in a related art nonvolatile memory technology, an area of the nonvolatile memory is increased when a select gate is selected considering a size of a memory cell. Therefore, only a few ranking semiconductor corporations can mass-manufacture the nonvolatile memory due to sophisticated manufacturing process steps. Accordingly, it is most important to minimize the size of the nonvolatile memory and to simplify the manufacturing process steps.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for manufacturing a nonvolatile memory that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for manufacturing a vertical nonvolatile memory having two trenches to minimize size.
Another object of the present invention is provide a method for manufacturing a nonvolatile memory using a reduced number of masks, thereby simplifying manufacturing processing.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will apparent from the description, or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for manufacturing a nonvolatile memory includes forming a first trench of a first width in a substrate of a first conductivity type, forming a second trench within the first trench, having a second width smaller than the first width of the first trench, injecting ions into a surface of the substrate and into sidewalls of the first and second trenches to adjust a threshold voltage, forming first insulating film sidewalls on the sidewalls of the first and second trenches, forming source and drain regions by injecting second conductive impurity ions into the substrate and bottom surfaces of the first and second trenches, depositing a second insulating film on the substrate, forming a floating gate and a gate electrode on sidewalls of the second insulating film within the first and second trenches, depositing a third insulating film on the substrate, and forming a control gate on sidewalls of the third insulating film at a sidewall of the first trench.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5616510 (1997-04-01), Wong
patent: 5773343 (1998-06-01), Lee et al.
patent: 6093606 (2000-07-01), Lin et al.
patent: 6127226 (2000-10-01), Lin et al.
patent: 6239465 (2001-05-01), Nakagawa
patent: 2001/0029077 (2001-10-01), Noble et al.
Booth Richard
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
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