Method for manufacturing a multi-bit memory cell

Details Method for manufacturing a multi-bit memory cell Method for manufacturing a multi-bit memory cell

2005-11-01

2005-11-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000, C438S954000

Reexamination Certificate

active

06960505

ABSTRACT:
A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5768192 (1998-06-01), Eitan
patent: 5796140 (1998-08-01), Tomioka
patent: 5877523 (1999-03-01), Liang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6348380 (2002-02-01), Weimer et al.
patent: 6574143 (2003-06-01), Nakazato
patent: 2000058680 (2000-02-01), None
patent: WO 99/49518 (1999-09-01), None

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