Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-06-14
2011-06-14
Smith, Matthew S (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S745000, C438S694000, C438S243000, C438S682000, C977S938000, C977S762000
Reexamination Certificate
active
07960235
ABSTRACT:
A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact. The present invention eliminates self-heating effect and floating-body effect, and is easy to integrate. The present invention is also advantageous in suppression of short channel effect and enables the size of the MOSFET to be smaller.
REFERENCES:
patent: 7749905 (2010-07-01), Cohen et al.
patent: 7816275 (2010-10-01), Fuller et al.
Song Yi
Xu Qiuxia
Zhou Huajie
Baptiste Wilner Jean
Institute of Microelectronics, Chinese Academy
Schwegman Lundberg & Woessner, P.A.
Smith Matthew S
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