Method for manufacturing a MOS transistor having reduced 1/f...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S290000

Reexamination Certificate

active

07018880

ABSTRACT:
The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.

REFERENCES:
patent: 5831319 (1998-11-01), Pan
patent: 6191463 (2001-02-01), Mitani et al.
patent: 6403422 (2002-06-01), Arita et al.
Natallya Lukyanchikova, et al., “The Influence of BF2 and F Implants on the 1/f Noise in SIGe HBTs With a Self-Aligned Link Base”; IEEE Transaction on Electron Devices, vol. 48, No. 12, Dec. 2001; pp. 2808-2815.
Yael Nemirovsky; “1/f Noise in CMOS Transistors for Analog Applications”; IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001; pp. 921-927.
A. Balasinski, et al.; “Fluorinated CMOSFETS Fabricated on (100) and (111) SI Substrates”; 1993 VLSITSA; pp. 95-99.
I.C Chen, et al.; “Performance and Reliability Enhancement for CVD Tungsten Polycided CMOS Transistors Due to Fluorine Incorporation in the Gate Oxide”; IEEE Electron Device Letters, vol. 15; No. 9, Sep. 1994.

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