Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-18
2003-01-21
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S595000
Reexamination Certificate
active
06509238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a method for manufacturing a MOS (referred to as MOS hereafter) device with improved well control stability.
2. Description of the Prior Art
Offset spacers are used in semiconductor devices. The Offset spacers can benefit the process window of photolithography and allow the realization of smaller cell size and therefore smaller chip size.
FIGS. 1A through 1C
illustrate, in cross-section, the conventional offset spacers process. This process begins by providing a semiconductor substrate
10
having a gate electrode
12
. The gate electrode
12
includes a gate oxide layer
14
and a conducting gate
16
as shown in FIG.
1
A. The conducting gate
16
is typically a polysilicon (poly) gate.
Next, as shown in
FIG. 1B
, offset spacers
18
are formed on sidewalls of the gate electrode
14
. The offset spacers
18
typically have a fixed width, such as
150
angstroms.
As shown in
FIG. 1C
, source and drain extensions
20
are formed in the semiconductor substrate
10
by ion implantation. Spacers
22
are formed on sidewalls of the gate electrode
12
. Source and drain regions
24
are formed in the semiconductor substrate
10
by ion implantation.
However, the channel length of the device is fixed after poly etching and the critical dimension of the poly gate is not easily controlled by the patterning process beyond 0.13 &mgr;m. In addition, since the critical dimension of the poly gate is not precise, electric characteristics are unstable and can not be remedied. Thus, the minimization of the feature size can not be achieved.
SUMMARY OF THE INVENTION
An object according to the present invention is to provide a method for manufacturing a MOS device with improved well control stability characterized by improvement of electric characteristics of the device.
The present invention achieves the above-indicated object by providing a method for determining conducting gate spacer thickness to well control MOS device stability comprising the steps of: providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.
REFERENCES:
patent: 6136616 (2000-10-01), Fulford et al.
patent: 6187645 (2001-02-01), Lin et al.
patent: 6294432 (2001-09-01), Lin et al.
patent: 2002/0090771 (2002-07-01), Lin
patent: 2002/0132377 (2002-09-01), Conchieri et al.
Chen Lung
Hsue Chen-Chiu
Wang Teng-Feng
Merchant & Gould
Nguyen Tuan H.
Silicon Integrated SAystems Corp.
Tingkang Xia Tim
LandOfFree
Method for manufacturing a MOS device with improved well... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a MOS device with improved well..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a MOS device with improved well... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3044206