Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-26
2001-10-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S723000
Reexamination Certificate
active
06297116
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a method for manufacturing a metal oxide semiconductor (MOS)-based structure, and more particularly to a method for preventing the loss of devices on the wafer during the process for fabricating an MOS transistor.
BACKGROUND OF THE INVENTION
Currently, in the manufacturing process of metal oxide semiconductor (MOS), a lightly doped drain (LDD) is often used to prevent the short channel effect. Please refer to
FIGS. 1
a
~
1
f
which are schematic diagrams showing a conventional process for manufacturing an MOS transistor with a lightly doped drain. In
FIG. 1
a
, a field oxide
103
, a gate oxide
101
, and a polysilicon layer
102
(serving as a gate) are formed on the silicon substrate
100
in sequence. Thereafter, a silicon dioxide
104
is formed over the silicon substrate
100
and the gate
102
by thermal oxidation as shown in
FIG. 1
b
and then an ion implantation is performed to form a lightly doped drain
105
in the silicon substrate
100
by using the gate
102
as a mask, shown in
FIG. 1
c
. In
FIG. 1
d
, a silicon dioxide layer
106
is deposited on the surface of the wafer by plasma enhanced chemical vapor deposition (PECVD) and then etched by an anisotropic etch to form spacers
107
alongside the gate
102
(shown in
FIG. 1
e
). The spacers can be used as a mask for the subsequent heavily doped implantation. Finally, after heavily doping the lightly doped drain
105
, a lightly doped region
108
and a heavily doped region
109
are formed as shown in
FIG. 1
f
and serve as a drain and a source.
However, during the etching process for forming the spacers, an over-etched situation may be happened, thereby resulting in a loss of the surfaces of the field oxide
103
and the lightly doped drain structure
105
9
(designated by an imaginary line shown in
FIG. 1
e
). For a small-size device, a shallow junction may prevent the short channel effect and punch through problem, but the above-described etching process for forming the spacers will seriously detract from the advantage of the shallow junction.
In addition, the size of the field oxide must be maintained to a certain degree in order to obtain a better isolation. However, this will cause that the device's size can not be effectively decreased. Therefore, it is tried by the Applicant to deal with the defects encountered by the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for manufacturing a metal oxide semiconductor (MOS)-based structure.
Another object of the present invention is to provide a method for preventing the loss of devices in a wafer.
According to the present invention, the method includes the steps of (a) providing a substrate, (b)forming a conducting layer on a portion of said substrate to serve as a gate, (c) forming an oxide layer over the conducting layer and an another portion of the substrate, (d) forming an etching stop layer over the oxide layer, (e) forming a lightly doped region in the another portion of the substrate, (f) forming spacers alongside the conducting layer and on a portion of the lightly doped region, and (g) implanting a dopant into an another portion of the lightly doped region for forming a drain and a source.
Preferably, the conducting layer is a polysilicon layer.
Certainly, the method further includes a step of forming a gate oxide between the conducting layer and the substrate.
The oxide layer is a silicon dioxide layer and formed by thermal oxidation.
Preferably, the etching stop layer is made of silicon nitride and has a thickness of about 150. It can be formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).
Certainly, the spacers are formed by forming an insulating layer on the etching stop layer and the conducting layer and partially removing the insulating layer by an anisotropic etch while retaining a portion of the insulating layer alongside the conducting layer to serve as the spacers.
Certainly, the substrate further includes a field oxide. The ratio of the etching selectivity of the etching stop layer to that of the insulating layer is relatively high enough to prevent the lightly doped region and the field oxide from being lost during an etching process of forming the spacers.
Again, the lightly doped region is heavily doped by an ion implantation using the spacers as masks to obtain two doped regions with different concentrations of dopant to serve as a drain and a source. Certainly, the lightly doped region can be a p-type or n-type lightly doped drain (LDD).
In addition, the method further includes steps of (1) forming an intermediate layer over the etching stop layer, the spacers, and the conducting layer; (2) partially removing the intermediate layer to form a contact window and expose a portion of the etching stop layer; (3) removing the portion of the etching stop layer to expose a portion of the oxide layer in the contact window; (4) performing a reflow process of the intermediate layer; and (5) removing the portion of the oxide layer to expose the lightly doped region in the contact window and forming a metal layer in the contact window and over the exposed lightly doped region.
Preferably, the intermediate layer is made of borophosphosilicate glass (BPSG) and the metal layer can be formed by a sputtering process.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
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Klein & Szekeres LLP
Lindsay Jr. Walter L.
Niebling John F.
Winbond Electronics Corp.
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